A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. - Kuo-Hsing Cheng; Wei-Bin Yang; Shu-Chang Kuo (ISCAS (1), 2004)

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. - Wei-Bin Yang; Shu-Chang Kuo; Yuan-Hua Chu; Kuo-Hsing Cheng (ECCTD, 2005)

The new improved pseudo fractional-N clock generator with 50% duty cycle. - Shu-Chang Kuo; Tzu-Chien Hung; Wei-Bin Yang (ISCAS, 2006)

Collaborative voltage scaling with online STA and variable-latency datapath. - Tay-Jyi Lin; Pi-Chen Hsiao; Chi-Hung Lin; Shu-Chang Kuo; Chou-Kun Lin; Yu-Ting Kuo; Chih-Wei Liu; Yuan-Hua Chu (ACM Great Lakes Symposium on VLSI, 2010)