A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. - Wei-Chih Chen; Chien-Chun Tsai; Chih-Hsien Chang; Yung-Chow Peng; Fu-Lung Hsueh; Tsung-Hsin Yu; Jinn-Yeh Chien; Wen-Hung Huang; Chi-Chang Lu; Mu-Shan Lin; Chin-Ming Fu; Shu-Chun Yang; et al. (CICC, 2010)

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. - Mu-Shan Lin; Chien-Chun Tsai; Chih-Hsien Chang; Wen-Hung Huang; Ying-Yu Hsu; Shu-Chun Yang; Chin-Ming Fu; Mao-Hsuan Chou; Tien-Chien Huang; Ching-Fang Chen; Tze-Chiang Huang; Saman Adham; et al. (IEEE J. Solid State Circuits, 2014)

A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package. - Mu-Shan Lin; Chien-Chun Tsai; Kenny Cheng-Hsiang Hsieh; Wen-Hung Huang; Yu-Chi Chen; Shu-Chun Yang; Chin-Ming Fu; Hao-Jie Zhan; Jinn-Yeh Chien; Shao-Yu Li; Y.-H. Chen; C.-C. Kuo; et al. (Hot Chips Symposium, 2016)

A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. - Wei-Chih Chen; Shu-Chun Yang; Yu-Nan Shih; Wen-Hung Huang; Chien-Chun Tsai; Kenny Cheng-Hsiang Hsieh (VLSI Circuits, 2019)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

Dog nose-print recognition based on the shape and spatial features of scales. - Yung-Kuan Chan; Chuen-Horng Lin; Yuan-Rong Ben; Ching-Lin Wang; Shu-Chun Yang; Meng-Hsiun Tsai; Shyr-Shen Yu (Expert Syst. Appl., 2024)

Dog identification based on textural features and spatial relation of noseprint. - Yung-Kuan Chan; Chuen-Horng Lin; Ching-Lin Wang; Keng-Chang Tu; Shu-Chun Yang; Meng-Hsiun Tsai; Shyr-Shen Yu (Pattern Recognit., 2024)

UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies. - Yu-Jie Huang; Mu-Shan Lin; Chien-Chun Tsai; Wei-Chih Chen; Hsin-Hung Kuo; Shu-Chun Yang; Shenggao Li (CICC, 2025)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)