A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. - Ming-Hung Chang; Yi-Te Chiu; Shu-Lin Lai; Wei Hwang (ISLPED, 2011)

0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. - Po-Tsang Huang; Shu-Lin Lai; Ching-Te Chuang; Wei Hwang; Jason Huang; Angelo Hu; Paul Kan; Michael Jia; Kimi Lv; Bright Zhang (A-SSCC, 2014)