Multiplier architecture power consumption characterization for low-power DSP applications. - Sangjin Hong; Shu-Shin Chin; Suhwan Kim 001; Wei Hwang (ICECS, 2002)

Glitching power reduction through supply voltage adaptation mechanism for low power array structure design. - Sangjin Hong; Shu-Shin Chin; Magesh Sadasivam (ISCAS (2), 2004)

Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. - Shu-Shin Chin; Sangjin Hong; Suhwan Kim 001 (ISVLSI, 2004)

Incorporating Power Reduction Mechanism in Arithmetic Core Design. - Sangjin Hong; Shu-Shin Chin (ISVLSI, 2004)

Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. - Sangjin Hong; Shu-Shin Chin; Suhwan Kim 001; Wei Hwang (J. VLSI Signal Process., 2004)

Extensible supply voltage control mechanism for low power array structure design. - Sangjin Hong; Shu-Shin Chin (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications. - Sangjin Hong; Shu-Shin Chin (J. VLSI Signal Process., 2005)

Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters. - Sangjin Hong; Shu-Shin Chin; Petar M. Djuric; Miodrag Bolic (J. VLSI Signal Process., 2006)