Case study of process and design performance debugging with Digital Speed Sensor. - Chao-Wen Tzeng; Yin-Yen Chen; Jih-Nung Lee; Shu-Yi Kao (VLSI-DAT, 2015)

Non-regression approach for the behavioral model generator in mixed-signal system verification. - Ling-Yen Song; Chun Wang; Chien-Nan Jimmy Liu; Yun-Jing Lin; Meng-Jung Lee; Yu-Lan Lo; Shu-Yi Kao (VLSI-SoC, 2017)

A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks*. - Yi-Cheng Zhao; Yu-Chieh Lin; Ting-Chi Wang; Ting-Hsiung Wang; Yun-Ru Wu; Hsin-Chang Lin; Shu-Yi Kao (DATE, 2019)

Layout-Based Dual-Cell-Aware Tests. - Tse-Wei Wu; Dong-Zhen Lee; Yu-Hao Huang; Mango C.-T. Chao; Kai-Chiang Wu; Shu-Yi Kao; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee (VTS, 2019)

CNN-based Stochastic Regression for IDDQ Outlier Identification. - Chun-Teng Chen; Chia-Heng Yen; Cheng-Yen Wen; Cheng-Hao Yang; Kai-Chiang Wu; Mason Chern; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (VTS, 2020)

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. - Cheng-Hao Yang; Chia-Heng Yen; Ting-Rui Wang; Chun-Teng Chen; Mason Chern; Ying-Yen Chen; Jih-Nung Lee; Shu-Yi Kao; Kai-Chiang Wu; Mango Chia-Tso Chao (VTS, 2021)

Methodology of Generating Timing-Slack-Based Cell-Aware Tests. - Yu-Teng Nien; Kai-Chiang Wu; Dong-Zhen Lee; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

CNN-Based Stochastic Regression for IDDQ Outlier Identification. - Chia-Heng Yen; Chun-Teng Chen; Cheng-Yen Wen; Ying-Yen Chen; Jih-Nung Lee; Shu-Yi Kao; Kai-Chiang Wu; Mango Chia-Tso Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)