A difference detector PFD for low jitter PLL. - Kuo-Hsing Cheng; Tse-Hua Yao; Shu-Yu Jiang; Wei-Bin Yang (ICECS, 2001)

BIST for clock jitter measurements. - Kuo-Hsing Cheng; Shu-Yu Jiang; Zong-Shen Chen (ISCAS (5), 2003)

Static divided word matching line for low-power Content Addressable Memory design. - Kuo-Hsing Cheng; Chia-Hung Wei; Shu-Yu Jiang (ISCAS (2), 2004)

A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. - Kuo-Hsing Cheng; Shu-Ming Chang; Shu-Yu Jiang; Wei-Bin Yang (ISCAS (2), 2005)

Self-sampled vernier delay line for built-in clock jitter measurement. - Kuo-Hsing Cheng; Chan-Wei Huang; Shu-Yu Jiang (ISCAS, 2006)

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. - Shu-Yu Jiang; Chan-Wei Huang; Yu-Lung Lo; Kuo-Hsing Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver. - Shu-Yu Jiang; Kuo-Hsing Cheng; Pei-Yi Jian (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. - Kuo-Hsing Cheng; Jen-Chieh Liu; Chih-Yu Chang; Shu-Yu Jiang; Kai-Wei Hong (IEEE Trans. Very Large Scale Integr. Syst., 2011)