A Ratio-independent and Gain-insensitive Algorithmic Analog-to-digital Converter. - Shu-Yuan Chin; Chung-Yu Wu (ISCAS, 1993)

An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle. - Shu-Yuan Chin; Chung-Yu Wu (ISCAS, 1994)

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources. - Shu-Yuan Chin; Chung-Yu Wu (IEEE J. Solid State Circuits, 1994)

A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter. - Shu-Yuan Chin; Chung-Yu Wu (IEEE J. Solid State Circuits, 1996)