Shuai Mu

According to our database1, Shuai Mu authored at least 13 papers between 2009 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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On csauthors.net:

Bibliography

2017
Toward Real-Time Ray Tracing: A Survey on Hardware Acceleration and Microarchitecture Techniques.
ACM Comput. Surv., 2017

2015
GPU accelerated sparse matrix-vector multiplication and sparse matrix-transpose vector multiplication.
Concurrency and Computation: Practice and Experience, 2015

2014
Orchestrating Cache Management and Memory Scheduling for GPGPU Applications.
IEEE Trans. VLSI Syst., 2014

Toward Concurrent Lock-Free Queues on GPUs.
IEICE Transactions, 2014

Performance Optimization for Sparse AtAx in Parallel on Multicore CPU.
IEICE Transactions, 2014

Atomic reduction based sparse matrix-transpose vector multiplication on GPUs.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

2013
Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUs.
IEICE Transactions, 2013

Electronic Design Automation with Graphic Processors: A Survey.
Foundations and Trends in Electronic Design Automation, 2013

FastLanes: An FPGA accelerated GPU microarchitecture simulator.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Towards accelerating irregular EDA applications with GPUs.
Integration, 2012

2011
Evaluating the potential of graphics processors for high performance embedded computing.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
IP routing processing with graphic processors.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Taming irregular EDA applications on GPUs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009


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