Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. - Jie S. Hu; Greg M. Link; Johnsy K. John; Shuai Wang 006; Sotirios G. Ziavras (Asia-Pacific Computer Systems Architecture Conference, 2005)

In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. - Jie S. Hu; Shuai Wang 006; Sotirios G. Ziavras (DSN, 2006)

On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (ICSAMOS, 2006)

Asymmetrically Banked Value-Aware Register Files. - Shuai Wang 006; Hongyan Yang; Jie S. Hu; Sotirios G. Ziavras (ISVLSI, 2007)

Vector Processing Support for FPGA-Oriented High Performance Applications. - Hongyan Yang; Shuai Wang 006; Sotirios G. Ziavras; Jie S. Hu (ISVLSI, 2007)

BTB Access Filtering: A Low Energy and High Performance Design. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (ISVLSI, 2008)

Asymmetrically banked value-aware register files for low-energy and high-performance. - Shuai Wang 006; Hongyan Yang; Jie S. Hu; Sotirios G. Ziavras (Microprocess. Microsystems, 2008)

Self-Adaptive Data Caches for Soft-Error Reliability. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Exploiting narrow-width values for thermal-aware register file designs. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras; Sung Woo Chung (DATE, 2009)

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IEEE Trans. Computers, 2009)

On the Exploitation of Narrow-Width Values for Improving Register File Reliability. - Jie S. Hu; Shuai Wang 006; Sotirios G. Ziavras (IEEE Trans. Very Large Scale Integr. Syst., 2009)

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (ISVLSI, 2010)

Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. - Li Tang 007; Shuai Wang 006; Jie S. Hu; Xiaobo Sharon Hu (ISVLSI, 2011)

Low power aging-aware register file design by duty cycle balancing. - Shuai Wang 006; Tao Jin; Chuanlei Zheng; Guangshan Duan (DATE, 2012)

Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors. - Chuanlei Zheng; Parijat Shukla; Shuai Wang 006; Jie S. Hu (DFT, 2012)

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IET Comput. Digit. Tech., 2012)

Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. - Shuai Wang 006; Jie S. Hu; Sotirios G. Ziavras (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Combating NBTI-induced aging in data caches. - Shuai Wang 006; Guangshan Duan; Chuanlei Zheng; Tao Jin (ACM Great Lakes Symposium on VLSI, 2013)

Exploiting narrow-width values for improving non-volatile cache lifetime. - Guangshan Duan; Shuai Wang 006 (DATE, 2014)

Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors. - Chuanlei Zheng; Shuai Wang 006 (DFT, 2014)

On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors. - Shuai Wang 006; Guangshan Duan (Microprocess. Microsystems, 2015)

Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing. - Shuai Wang 006; Tao Jin; Chuanlei Zheng; Guangshan Duan (J. Circuits Syst. Comput., 2016)

Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime. - Shuai Wang 006; Guangshan Duan; Yupeng Li; Qianhao Dong (ACM Trans. Design Autom. Electr. Syst., 2017)