Shuai Yuan

Orcid: 0000-0002-8942-0145

Affiliations:
  • Tsinghua University, Beijing, China


According to our database1, Shuai Yuan authored at least 30 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
DeepLight: Reconstructing High-Resolution Observations of Nighttime Light With Multi-Modal Remote Sensing Data.
CoRR, 2024

2023
MUREN: MUltistage Recursive Enhanced Network for Coal-Fired Power Plant Detection.
Remote. Sens., April, 2023

A review of individual tree crown detection and delineation from optical remote sensing images.
CoRR, 2023

An adaptive image fusion method for Sentinel-2 images and high-resolution images with long-time intervals.
Int. J. Appl. Earth Obs. Geoinformation, 2023

Achieving 10m China Land Cover Mapping within Three Minutes Using a New Sunway Supercomputer.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2023

CO-Detector: Towards Complex Object Detection with Cross-Part Feature Learning in Remote Sensing.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2023

Large-Scale Land Cover Mapping with Fine-Grained Classes via Class-Aware Semi-Supervised Semantic Segmentation.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

2022
A Two-Stage Adaptation Network (TSAN) for Remote Sensing Scene Classification in Single-Source-Mixed-Multiple-Target Domain Adaptation (S²M²T DA) Scenarios.
IEEE Trans. Geosci. Remote. Sens., 2022

Multisource-Domain Generalization-Based Oil Palm Tree Detection Using Very-High-Resolution (VHR) Satellite Images.
IEEE Geosci. Remote. Sens. Lett., 2022

A Parallel Approach for Oil Palm Tree Detection on a SW26010 Many-Core Processor.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

Srbuildingseg-E<sup>2</sup>: An Integrated Model for End-to-End Higher-Resolution Building Extraction.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

Melting Glacier: A 37-Year (1984-2020) High-Resolution Glacier-Cover Record of MT. Kilimanjaro.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

2021
Making Low-Resolution Satellite Images Reborn: A Deep Learning Approach for Super-Resolution Building Extraction.
Remote. Sens., 2021

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS.
IEEE Access, 2021

2020
Unsupervised Mixed Multi-Target Domain Adaptation for Remote Sensing Images Classification.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2020

2019
Large-Scale Oil Palm Tree Detection from High-Resolution Remote Sensing Images Using Faster-RCNN.
Proceedings of the 2019 IEEE International Geoscience and Remote Sensing Symposium, 2019

2018
A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.
IEEE J. Solid State Circuits, 2017

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 25Gb/s serial-link repeater with receiver equalization and transmitter de-emphasis in 0.13μm SiGe BiCMOS.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 50Gb/s repeater and 2 × 50Gb/s 27-1 PRBS generator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 10Gb/s analog equalizer in 0.18um CMOS.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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