NVP: A Flexible and Efficient Processor Architecture for Accelerating Diverse Computer Vision Tasks including DNN. - Ye Liu 011; Fei Wu; Neng Zhao; Qirong Zhang; Wenqiang Wang; Yutong Yang; Xiangting Li; Sixu Li; Zili Huang; Shuang Hao 005; Guangbin Ou; Liang Zhou; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

BOHA: A High Performance VSLAM Backend Optimization Hardware Accelerator Using Recursive Fine-Grain H-Matrix Decomposition and Early-Computing With Approximate Linear Solver. - Ye Liu 011; Kun Huang; Neng Zhao; Jingyuan Li; Shuang Hao 005; Zili Huang; Xiuyuan Qi; Xinghao Wang; Liang Zhou; Liang Chang 002; Jun Zhou 017 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An FPGA-based Ultra-High Performance and Scalable Optical Flow Hardware Accelerator for Autonomous Driving. - Ye Liu 011; Shuang Hao 005; Kun Huang; Minghui Yang; Zili Huang; Xiuyuan Qi; Yiting Li; Liang Zhou; Yu Long 005; Jun Zhou 017 (ISCAS, 2024)

A High-Performance ORB Accelerator with Algorithm and Hardware Co-design for Visual Localization. - Xiuyuan Qi; Ye Liu 011; Shuang Hao 005; Zherong Liu; Kun Huang; Minghui Yang; Liang Zhou; Jun Zhou 011 (ISCAS, 2024)