Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks. - Shaoxia Fang; Lu Tian; Junbin Wang; Shuang Liang 010; Dongliang Xie; Zhongmin Chen; Lingzhi Sui; Qian Yu; Xiaoming Sun; Yi Shan; Yu Wang 002 (FPT, 2018)

Compressed CNN Training with FPGA-based Accelerator. - Kaiyuan Guo; Shuang Liang 010; Jincheng Yu; Xuefei Ning; Wenshuo Li; Yu Wang 002; Huazhong Yang (FPGA, 2019)

DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators. - Yu Xing; Shuang Liang 010; Lingzhi Sui; Zhen Zhang; Jiantao Qiu; Xijie Jia; Xin Liu; Yushun Wang; Yi Shan; Yu Wang 002 (FPGA, 2019)

A Fine-Grained Sparse Accelerator for Multi-Precision DNN. - Shulin Zeng; Yujun Lin 001; Shuang Liang 010; Junlong Kang; Dongliang Xie; Yi Shan; Song Han 003; Yu Wang 002; Huazhong Yang (FPGA, 2019)

On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA. - Yiming Hu; Shuang Liang 010; Jincheng Yu; Yu Wang 002; Huazhong Yang (ISVLSI, 2019)

A Surgery of the Neural Architecture Evaluators. - Xuefei Ning; Wenshuo Li; Zixuan Zhou; Tianchen Zhao; Yin Zheng; Shuang Liang 010; Huazhong Yang; Yu Wang 002 (CoRR, 2020)

BARS: Joint Search of Cell Topology and Layout for Accurate and Efficient Binary ARchitectures. - Tianchen Zhao; Xuefei Ning; Songyi Yang; Shuang Liang 010; Peng Lei; Jianfei Chen; Huazhong Yang; Yu Wang 002 (CoRR, 2020)

aw_nas: A Modularized and Extensible NAS framework. - Xuefei Ning; Changcheng Tang; Wenshuo Li; Songyi Yang; Tianchen Zhao; Niansong Zhang; Tianyi Lu; Shuang Liang 010; Huazhong Yang; Yu Wang 002 (CoRR, 2020)

DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators. - Yu Xing; Shuang Liang 010; Lingzhi Sui; Xijie Jia; Jiantao Qiu; Xin Liu; Yushun Wang; Yi Shan; Yu Wang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Computing Platform Design for Autonomous Driving Systems. - Shuang Liang 010; Changcheng Tang; Xuefei Ning; Shulin Zeng; Jincheng Yu; Yu Wang 002; Kaiyuan Guo; Diange Yang; Tianyi Lu; Huazhong Yang (ASP-DAC, 2021)

Evaluating Efficient Performance Estimators of Neural Architectures. - Xuefei Ning; Changcheng Tang; Wenshuo Li; Zixuan Zhou; Shuang Liang 010; Huazhong Yang; Yu Wang 002 (NeurIPS, 2021)

Multi-Agent Vulnerability Discovery for Autonomous Driving with Hazard Arbitration Reward. - Weilin Liu; Ye Mu; Chao Yu 005; Xuefei Ning; Zhong Cao; Yi Wu 013; Shuang Liang 010; Huazhong Yang; Yu Wang 002 (CoRR, 2021)

Efficient Autonomous Driving System Design: From Software to Hardware. - Yu Wang 002; Shulin Zeng; Kaiyuan Guo; Xuefei Ning; Yali Zhao; Zhongyuan Qiu; Changcheng Tang; Shuang Liang 010; Huazhong Yang (ISVLSI, 2022)

TA-GATES: An Encoding Scheme for Neural Network Architectures. - Xuefei Ning; Zixuan Zhou; Junbo Zhao 001; Tianchen Zhao; Yiping Deng; Changcheng Tang; Shuang Liang 010; Huazhong Yang; Yu Wang 002 (NeurIPS, 2022)

Multi-Agent Vulnerability Discovery for Autonomous Driving Policy by Finding AV-Responsible Scenarios. - Ye Mu; Weilin Liu; Chao Yu 005; Xuefei Ning; Zhong Cao; Zelai Xu; Shuang Liang 010; Huazhong Yang; Yu Wang 005 (CASE, 2024)