Low power implementation of an n-tone Sigma Delta converter. - Shubha Bommalingaiahnapallya; Ramesh Harjani (ISCAS (1), 2004)

Process tolerant design of N-tone Sigma-Delta converters. - Shubha Bommalingaiahnapallya; Ramesh Harjani (ISCAS (5), 2005)

Power optimized LC VCO and mixer co-design. - Byunghoo Jung; Shubha Bommalingaiahnapallya; Ramesh Harjani (ISCAS (5), 2005)

High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator. - Shubha Bommalingaiahnapallya; Kin-Joe Sham; Mahmoud Reza Ahmadi; Ramesh Harjani (ISCAS, 2007)

A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator. - Kin-Joe Sham; Shubha Bommalingaiahnapallya; Mahmoud Reza Ahmadi; Ramesh Harjani (IEEE Trans. Circuits Syst. II Express Briefs, 2008)