Approximation through logic isolation for the design of quality configurable circuits. - Shubham Jain 004; Swagath Venkataramani; Anand Raghunathan (DATE, 2016)

Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. - Shubham Jain 004; Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Pierce Chuang; Leland Chang (DAC, 2018)

Computing-in-memory with spintronics. - Shubham Jain 004; Sachin S. Sapatnekar; Jianping Wang 006; Kaushik Roy 001; Anand Raghunathan (DATE, 2018)

Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars. - Shubham Jain 004; Abhronil Sengupta; Kaushik Roy 001; Anand Raghunathan (CoRR, 2018)

Computing in Memory With Spin-Transfer Torque Magnetic RAM. - Shubham Jain 004; Ashish Ranjan 001; Kaushik Roy 001; Anand Raghunathan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automatic Synthesis Techniques for Approximate Circuits. - Ashish Ranjan 001; Swagath Venkataramani; Shubham Jain 004; Younghoon Kim; Shankar Ganesh Ramasubramanian; Arnab Raha; Kaushik Roy 001; Anand Raghunathan (Approximate Circuits, 2019)

BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks. - Shubham Jain 004; Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Kailash Gopalakrishnan; Leland Chang (DAC, 2019)

X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks. - Ashish Ranjan 001; Shubham Jain 004; Jacob R. Stevens; Dipankar Das 002; Bharat Kaul; Anand Raghunathan (DAC, 2019)

Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation. - Sandeep Krishna Thirumala; Shubham Jain 004; Anand Raghunathan; Sumeet Kumar Gupta (ISLPED, 2019)

Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support. - Sandeep Krishna Thirumala; Yi-Tse Hung; Shubham Jain 004; Arnab Raha; Niharika Thakuria; Vijay Raghunathan; Anand Raghunathan; Zhihong Chen; Sumeet Kumar Gupta (CoRR, 2019)

Neural network accelerator design with resistive crossbars: Opportunities and challenges. - Shubham Jain 004; Aayush Ankit; Indranil Chakraborty; Tayfun Gokmen; Malte J. Rasch; Wilfried Haensch; Kaushik Roy 001; Anand Raghunathan (IBM J. Res. Dev., 2019)

SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks. - Sanchari Sen; Shubham Jain 004; Swagath Venkataramani; Anand Raghunathan (IEEE Trans. Computers, 2019)

Emerging Neural Workloads and Their Impact on Hardware. - David Brooks 001; Martin M. Frank; Tayfun Gokmen; Udit Gupta; Xiaobo Sharon Hu; Shubham Jain 004; Ann Franchesca Laguna; Michael T. Niemier; Ian O'Connor; Anand Raghunathan; Ashish Ranjan 001; Dayane Reis; et al. (DATE, 2020)

Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks. - Sandeep Krishna Thirumala; Shubham Jain 004; Sumeet Kumar Gupta; Anand Raghunathan (DATE, 2020)

Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges. - Indranil Chakraborty; Mustafa Fayez Ali; Aayush Ankit; Shubham Jain 004; Sourjya Roy; Shrihari Sridharan; Amogh Agrawal; Anand Raghunathan; Kaushik Roy 001 (Proc. IEEE, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain 004; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems. - Shubham Jain 004; Anand Raghunathan (ACM Trans. Embed. Comput. Syst., 2020)

TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks. - Shubham Jain 004; Sumeet Kumar Gupta; Anand Raghunathan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Design Tools for Resistive Crossbar based Machine Learning Accelerators. - Indranil Chakraborty; Sourjya Roy; Shrihari Sridharan; Mustafa Fayez Ali; Aayush Ankit; Shubham Jain 004; Anand Raghunathan (AICAS, 2021)

A Framework for Adaptive Deep Reinforcement Semantic Parsing of Unstructured Data. - Shubham Jain 004; Amy de Buitléir; Enda Fallon (ICTC, 2021)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain 004; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars. - Shubham Jain 004; Abhronil Sengupta; Kaushik Roy 001; Anand Raghunathan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems. - Sourjya Roy; Shrihari Sridharan; Shubham Jain 004; Anand Raghunathan (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration. - Reena Elangovan; Shubham Jain 004; Anand Raghunathan (ACM Trans. Design Autom. Electr. Syst., 2022)

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited). - Martin M. Frank; Ning Li; Malte J. Rasch; Shubham Jain 004; Ching-Tzu Chen; Ramachandran Muralidhar; Jin-Ping Han; Vijay Narayanan; Timothy Philip; Kevin Brew; Andrew Simon; Iqbal Saraf; et al. (IRPS, 2023)

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). - Hsinyu Tsai; Pritish Narayanan; Shubham Jain 004; Stefano Ambrogio; Kohji Hosokawa; Masatoshi Ishii; Charles Mackin; Ching-Tzu Chen; Atsuya Okazaki; Akiyo Nomura; Irem Boybat; Ramachandran Muralidhar; et al. (ISCAS, 2023)

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. - Shubham Jain 004; Hsinyu Tsai; Ching-Tzu Chen; Ramachandran Muralidhar; Irem Boybat; Martin M. Frank; Stanislaw Wozniak; Milos Stanisavljevic; Praneet Adusumilli; Pritish Narayanan; Kohji Hosokawa; Masatoshi Ishii; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU. - Sanchari Sen; Shubham Jain 004; Sarada Krithivasan; Swagath Venkataramani; Vijayalakshmi Srinivasan (IEEE Micro, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)

CiMBA: Accelerating Genome Sequencing Through On-Device Basecalling via Compute-in-Memory. - William Andrew Simon; Irem Boybat; Riselda Kodra; Elena Ferro; Gagandeep Singh 002; Mohammed Alser; Shubham Jain 004; Hsinyu Tsai; Geoffrey W. Burr; Onur Mutlu; Abu Sebastian (IEEE Trans. Parallel Distributed Syst., 2025)