A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference. - Shubin Liu 001; Zhangming Zhu; Huaxi Gu; Minjie Liu; Lianxi Liu; Yintang Yang (IEICE Electron. Express, 2012)

A low-jitter pulsewidth control loop with high supply noise rejection. - Shubin Liu 001; Zhangming Zhu; Huaxi Gu; Yintang Yang (IEICE Electron. Express, 2013)

A Low Offset Comparator for High Speed Low Power ADC. - Zhangming Zhu; Weitie Wang; Yuheng Guan; Shubin Liu 001; Yu Xiao; Lianxi Liu; Yintang Yang (J. Circuits Syst. Comput., 2013)

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS. - Wei Guo 031; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2016)

An automatic mode low-jitter pulsewidth control loop with broadband operation frequency. - Shubin Liu 001; Wei Guo 031; Zhangming Zhu (Microelectron. J., 2016)

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS. - Yi Shen 007; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2016)

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching. - Shubin Liu 001; Yi Shen 007; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Analysis and optimal distribution scheme for SAR-VCO ADCs. - Ruixue Ding; Hongzhi Liang; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2017)

A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage. - Jingyu Wang 003; Zhangming Zhu; Shubin Liu 001; Ruixue Ding (Microelectron. J., 2017)

A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application. - Jin Hu 006; Maliang Liu; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (APCCAS, 2018)

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs. - Hongzhi Liang; Ruixue Ding; Shubin Liu 001; Zhangming Zhu (J. Circuits Syst. Comput., 2018)

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC. - Yi Shen 007; Zhangming Zhu; Shubin Liu 001; Yintang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique. - Jingyu Wang 003; Shubin Liu 001; Yi Shen 007; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique. - Shubin Liu 001; Zhangming Zhu; Jingyu Wang 003; Lianxi Liu; Yintang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS. - Yi Xie; Yuhua Liang; Maliang Liu; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. - Xiyuan Tang; Yi Shen 007; Xin Xin 005; Shubin Liu 001; Jueping Cai; Zhangming Zhu; Nan Sun 001 (VLSI Circuits, 2020)

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. - Yi Shen 007; Xiyuan Tang; Linxiao Shen; Wenda Zhao 002; Xin Xin 005; Shubin Liu 001; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 7b 400 ​MS/s pipelined SAR ADC in 65 ​nm CMOS. - Ruixue Ding; Li Dang; Hanchao Lin; Depeng Sun; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2020)

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier. - Shubin Liu 001; Haolin Han; Yi Shen 007; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator. - Yanbo Zhang; Shubin Liu 001; Binbin Tian; Yan Zhu 001; Chi-Hang Chan; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS. - Jin Zhang 034; Xiaoqian Ren; Shubin Liu 001; Chi-Hang Chan; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. - Yanbo Zhang; Jin Zhang 034; Shubin Liu 001; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2021)

A 2.6 GΩ, 1.4 μVrms current-reuse instrumentation amplifier for wearable electrocardiogram monitoring. - Wenfei Cao; Yi Liu 060; Shubin Liu 001; Ling Wang; Rui Ma 007; Zhangming Zhu (Microelectron. J., 2021)

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs. - Dengquan Li; Maliang Liu; Shubin Liu 001; Yuhua Liang; Ruixue Ding (Microelectron. J., 2021)

A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems. - Jian Liu; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower. - Tian Feng; Dengquan Li; Jiale Ding; Shubin Liu 001; Yi Shen 007; Zhangming Zhu (ICTA, 2022)

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs. - Jiale Ding; Yukai Huang; Dengquan Li; Shubin Liu 001; Yi Shen 007; Zhangming Zhu (Circuits Syst. Signal Process., 2022)

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. - Yanbo Zhang; Jin Zhang 034; Shubin Liu 001; Ruixue Ding; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

An efficient EEGNet processor design for portable EEG-Based BCIs. - Lichen Feng; Liying Yang 001; Shubin Liu 001; Chenxi Han; Yueqi Zhang; Zhangming Zhu (Microelectron. J., 2022)

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration. - Yukai Huang; Jiale Ding; Dengquan Li; Xin Zhao 035; Shubin Liu 001; Yi Shen 007; Zhangming Zhu (Microelectron. J., 2022)

Radio frequency analog-to-digital converters: Systems and circuits review. - Dengquan Li; Xin Zhao 035; Shubin Liu 001; Maliang Liu; Ruixue Ding; Yuhua Liang; Zhangming Zhu (Microelectron. J., 2022)

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS. - Henghui Mao; Dengquan Li; Shubin Liu 001 (Microelectron. J., 2022)

Capacitance-to-voltage converter employing parallel-series passive charge integrator for low noise power efficient MEMS capacitive sensor. - Longjie Zhong; Pengpeng Shang; Wenfei Cao; Zhangming Zhu; Shubin Liu 001 (Microelectron. J., 2022)

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems. - Yuhua Liang; Changying Li; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Biomed. Circuits Syst., 2022)

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS. - Maliang Liu; Chenxi Zhang; Shubin Liu 001; Dengquan Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. - Yi Shen 007; Xiyuan Tang; Xin Xin 005; Shubin Liu 001; Zhangming Zhu; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer. - Longjie Zhong; Shubin Liu 001; Donglai Xu; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs. - Depeng Sun; Ruixue Ding; Feng Bu; Hongzhi Liang; Dengquan Li; Yuhua Liang; Shubin Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.018 %/V Line Sensitivity Voltage Reference With -82.46 dB PSRR at 100 Hz for Bio-Potential Signals Readout Systems. - Kui Wen; Yuke Shen; Yongyuan Li; Shubin Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure. - Pinyun Yi; Yuhua Liang; Shubin Liu 001; Nuo Xu; Liang Fang; Yue Hao (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer. - Longjie Zhong; Shubin Liu 001; Donglai Xu (IEEE Trans. Instrum. Meas., 2022)

A 77.8dB-SNDR 25MHz-BW 2nd-order NS Pipelined SAR ADC with 4th-order Gain-Error-Shaping. - Guolong Fu; Shubin Liu 001; Li Tian; Zhangming Zhu; Yanbo Zhang (ASICON, 2023)

A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $ lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step. - Hongzhi Liang; Yi Shen 007; Jun Chang; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (A-SSCC, 2023)

A $142.8- mu text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping. - Yuke Shen; Shubin Liu 001; Kui Wen; Yanbo Zhang; Yi Shen 007; Ruixue Ding; Zhangming Zhu (A-SSCC, 2023)

An 83.6dB-SNDR 101.6dB-SFDR 4th-Order Noise-Shaping SAR with 2nd-Order Nonlinearity Error Shaping. - Yanbo Zhang; Xianghui Zhang; Li Tian; Shubin Liu 001; Zhangming Zhu (A-SSCC, 2023)

A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. - Zhicheng Dong 002; Shubin Liu 001; Xiaoteng Zhao; Baotian Hao; Hongzhi Liang; Haolin Han; Menghao Wang; Weijie Han; Zhangming Zhu (CICC, 2023)

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu 001; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong 002; Dengquan Li; Ruixue Ding; Zhangming Zhu (CICC, 2023)

A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. - Junyan Hao; Minglei Zhang; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping. - Yanbo Zhang; Junyan Hao; Shubin Liu 001; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 100- to- 10-kHz 5.4- to- 216- μW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS Capacitive Accelerometer. - Longjie Zhong; Shubin Liu 001; Pengpeng Shang; Wenfei Cao; Zhangming Zhu (IEEE J. Solid State Circuits, 2023)

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique. - Yi Shen 007; Jian Liu; Chenxi Han; Angyang Li; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier. - Longjie Zhong; Shubin Liu 001; Donglai Xu; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation. - Chenxi Han; Shubin Liu 001; Yuhao Zhang; Lichen Feng; Hongzhi Liang; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An offset and gain error calibration method in high-precision SAR ADCs. - Junyan Hao; Yi Shen 007; Angyang Li; Min Wang; Qing Zou; Zheng Qiu; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2023)

A 0.26 μVrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array. - Tingyu Wang; Kui Wen; Longjie Zhong; Shubin Liu 001 (Microelectron. J., 2023)

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS. - Dengquan Li; Xin Zhao 035; Yi Shen 007; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 44-μW, 91.3-dB SNDR DT Δ Σ Modulator With Second-Order Noise-Shaping SAR Quantizer. - Ling Wang; Shubin Liu 001; Yanbo Zhang; Longjie Zhong; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller. - Qiang Wu 014; Linjun Wu; Yongyuan Li; Xun Li; Zhixiong Di; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. - Yi Shen 007; Junyan Hao; Shubin Liu 001; Zeshuai An; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC. - Xin Zhao 035; Dengquan Li; Feida Wang; Yi Shen 007; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA. - Huanan Li; Shicheng Jia; Juntao Guan; Rui Lai; Shubin Liu 001; Zhangming Zhu (AICAS, 2024)

A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting. - Yiyao Huang; Guolong Fu; Xianghui Zhang; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu (APCCAS, 2024)

A 14b Calibration-Free Pipelined SAR ADC Using a Single-Stage Gain Boost FIA. - HaoYu Tian; Guolong Fu; Yuzhou Xiong; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu (APCCAS, 2024)

A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. - Zhicheng Dong 002; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Rong Zhou; Depeng Sun; Yong Chen 005; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (A-SSCC, 2024)

A 2.4 GHz Ultra-Low-Power Low-Voltage Temperature-Stable Transmitter for Biosensing Applications. - Linwei Wang; Rong Zhou; Shubin Liu 001; Zhangming Zhu (BioCAS, 2024)

A 737nA Always-On MEMS Gyroscope with 5.45ms Start-up Time Using Burst Mode PLL Technique. - Longjie Zhong; Chengyue Li; Shubin Liu 001; Mingsheng Zhong; Zhangming Zhu (CICC, 2024)

A 0.64mm2Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique. - Longjie Zhong; Pengpeng Shang; Shubin Liu 001; Wenfei Cao; Lichen Feng; Yuhua Liang; Zhangming Zhu (CICC, 2024)

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers. - Miao Zhang; Xianting Su; Zekai Yang; Zhicheng Dong 002; Weitan Huang; Menghao Wang; Yukui Yu; Xiaoteng Zhao; Shubin Liu 001; Zhangming Zhu (ICTA, 2024)

A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area. - Zhicheng Dong 002; Xiaoteng Zhao; Weitan Huang; Yuan Gao 011; Depeng Sun; Shubin Liu 001; Lihong Yang; Zhangming Zhu (ISCAS, 2024)

Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting. - Dengquan Li; Yexin Zhu; Longsheng Wang; Shubin Liu 001; Zhangming Zhu (ISCAS, 2024)

5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression. - Hao Xu 005; Junyan Bi; Tenghao Zou; Weitao He; Yaxin Zeng; Junjie Gu; Ziyang Jiao; Shubin Liu 001; Zhangming Zhu; Na Yan 004 (ISSCC, 2024)

A wide load-range OTA using a digitally assisted compensating technique. - Haolin Han; Shubin Liu 001; Yi Shen 007; Hongzhi Liang; Yue Cao; Longjie Zhong; Zhangming Zhu (Sci. China Inf. Sci., 2024)

A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS. - Shubin Liu 001; Chenxi Han; Xiaoteng Zhao; Yuhao Zhang; Shixin Li; Hongzhi Liang; Lihong Yang; Zhangming Zhu (Sci. China Inf. Sci., 2024)

A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique. - Zhangming Zhu; Jun Chang; Hongzhi Liang; Ruixue Ding; Shubin Liu 001 (Sci. China Inf. Sci., 2024)

A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping. - Guolong Fu; Yanbo Zhang; Yan Wang; Zhiyu Zhao; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2024)

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry. - Haolin Han; Ruili Ren; Yi Shen 007; Ruixue Ding; Shubin Liu 001; Hongzhi Liang (Microelectron. J., 2024)

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique. - Haolin Han; Jinwei Zhang; Ruili Ren; Yi Shen 007; Shubin Liu 001; Ruixue Ding (Microelectron. J., 2024)

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test. - Yiyao Huang; Guolong Fu; Xianghui Zhang; Yuzhou Xiong; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2024)

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS. - Yun Li; Yi Shen 007; Yue Cao; Mengtong Wu; Li Dang; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (Microelectron. J., 2024)

An auto-zeroing chopper-stabilized capacitively coupled instrumentation amplifier with 25-Vpp common-mode interference tolerance. - Jiacheng Liu; Yuke Shen; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (Microelectron. J., 2024)

An instrumentation amplifier with series switch pseudo resistor DC-servo loop realizing 0.16-Hz high-pass corner. - Jinze Song; Kui Wen; Ruixue Ding; Min Chen; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2024)

A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators. - Depeng Sun; Ruiqing Wang; Feng Bu; Yuan Gao 011; Xiaoteng Zhao; Ruixue Ding; Shubin Liu 001; Rong Zhou (Microelectron. J., 2024)

A chopper instrumentation amplifier with discrete-time compensation based on current generation unit to eliminate electrode DC offset. - Zichao Wang 008; Kui Wen; Ruixue Ding; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2024)

A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm. - Dengquan Li; Longsheng Wang; Yi Shen 007; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Instrum. Meas., 2024)

LUT-Assisted Particle Swarm Optimization-Based Bit-Weight Calibration for SAR ADCs. - Longsheng Wang; Dengquan Li; Yexin Zhu; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (IEEE Trans. Instrum. Meas., 2024)

A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration. - Junyan Hao; Yi Shen 007; Jin Zhang 034; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error. - Hongzhi Liang; Shubin Liu 001; Ruixue Ding; Yi Shen 007; Dengquan Li; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

High Power-Efficiency Readout Circuit for MEMS Capacitive Accelerometer. - Longjie Zhong; Leyang Xue; Xiangyi Deng; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications. - Rong Zhou; Linwei Wang; Jianhang Yang; Zhen Li; Xiaoteng Zhao; Shubin Liu 001 (Microelectron. J., 2024)

A wideband low power RF Receiver Front-End for Internet-of-Things applications. - Rong Zhou; Jianhang Yang; Linwei Wang; Xiaoteng Zhao; Shubin Liu 001; Depeng Sun (Microelectron. J., 2024)

A -64.3 dB THD, 26 nV/√ Hz Bio-Potential Readout Analog-Front-End Amplifier With a Gm-C Integrator-Implanted DC Servo Loop, and a Bulk-Driven Ripple Reduction Loop. - Kui Wen; Shubin Liu 001; Longjie Zhong; Yuke Shen; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs. - Li Dang; Shubin Liu 001; Ruixue Ding; Yi Shen 007; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC. - Haolin Han; Shubin Liu 001; Hongzhi Liang; Yi Shen 007; Jianyu Guo; Ruili Ren; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and -250.8-dB FOMPLL. - Depeng Sun; Linguo Huang; Rong Zhou; Feng Bu; Lisheng Chen; Xiaoteng Zhao; Ruixue Ding; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Wideband Input Buffer Based on Cascade Complementary Source Follower. - Dengquan Li; Tian Feng; Jiale Ding; Yi Shen 007; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping. - Yuke Shen; Shubin Liu 001; Kui Wen; Yanbo Zhang; Yi Shen 007; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor. - Zhicheng Dong 002; Shubin Liu 001; Xiaoteng Zhao; Baotian Hao; Xianting Su; Hongzhi Liang; Menghao Wang; Zhangming Zhu (IEEE J. Solid State Circuits, 2024)

A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter. - Jun Chang; Hongzhi Liang; Yixiao Luo; Zeyu Peng; Zhe Li; Yi Shen 007; Shubin Liu 001; Zhangming Zhu (CICC, 2025)

A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS. - Chenxi Han; Xiaoteng Zhao; Qi Zhang; Yuan Liu; Yuhao Zhang; Hongzhi Liang; Yukui Yu; Shubin Liu 001; Zhangming Zhu (CICC, 2025)

A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking. - Hongzhi Liang; Jun Chang; Yixiao Luo; Zeyu Peng; Weimin Zhou; Li Dang; Yue Cao; Haolin Han; Yi Shen 007; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (CICC, 2025)

An 18-Bit 183.9dB-FoMS, DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS. - Yuke Shen; Shubin Liu 001; Deao Wu; Kui Wen; Yanbo Zhang; Yi Shen 007; Zhangming Zhu (CICC, 2025)

24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier. - Yue Cao; Yi Shen 007; Shubin Liu 001; Haolin Han; Hongzhi Liang; Li Dang; Dengquan Li; Ruixue Ding; Zhangming Zhu (ISSCC, 2025)

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur. - Depeng Sun; Feng Bu; Qixian Ye; Shijie Li; Yuan Gao 011; Bowen Wang 001; Hao Xu 005; Na Yan 004; Shubin Liu 001; Zhangming Zhu (ISSCC, 2025)

A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed. - Xiaoteng Zhao; Yuhao Zhang; Hao Chang; Yilong Dong; Chenxi Han; Zekai Yang; Zhicheng Dong 002; Rong Zhou; Shubin Liu 001; Zhangming Zhu (ISSCC, 2025)

A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur. - Feng Bu; Ruixue Ding; Depeng Sun; Yuan Gao 011; Ruiqing Wang; Xiaoteng Zhao; Rong Zhou; Shubin Liu 001 (Microelectron. J., 2025)

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection. - Le Chen; Yi Shen 007; Ruixue Ding; Shubin Liu 001; Haolin Han (Microelectron. J., 2025)

Power-efficient SAR ADC with noise-reduction scheme based on kT/C noise cancellation and adaptive tracking averaging. - Anji Huang; Gefeng Zeng; Yi Shen 007; Angyang Li; Libo Qian; Qing Zou; Zheng Qiu; Min Wang; Shubin Liu 001; Ruixue Ding; Yinshui Xia; Zhangming Zhu (Microelectron. J., 2025)

The sampling network for a 16-channel time-interleaved ADC. - Pengfei Ji; Chengyuan Liu; Li Dang; Shaoxuan Li; Ruixue Ding; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2025)

A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units. - Jie Liu; Xianting Su; Zekai Yang; Zhicheng Dong 002; Chenxi Han; Xiaoteng Zhao; Shubin Liu 001 (Microelectron. J., 2025)

A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator. - Zekai Yang; Xiaoteng Zhao; Huajin Sun; Xianting Su; Zhicheng Dong 002; Yilong Dong; Yukui Yu; Hongzhi Liang; Shubin Liu 001 (Microelectron. J., 2025)

Load-driven inductive peaking design for broad band continuous-time linear equalizer. - Miao Zhang; Ruidong Li; Xiaoteng Zhao; Xianting Su; Zhicheng Dong 002; Zekai Yang; Hongyu Su; Hongzhi Liang; Yukui Yu; Shubin Liu 001 (Microelectron. J., 2025)

Exponential-incremental quantization-based calibration for capacitor mismatch in high-precision SAR ADCs. - Zheyu Zhang; Yuzhou Xiong; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2025)

A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer. - Bo Zhao 003; Yuke Shen; Tao Chen; Yi Shen 007; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (Microelectron. J., 2025)

A 10-bit 4 GS/s Pipelined-SAR ADC based on loop-unrolled and partial-interleaving. - Weimin Zhou; Zhe Li; Hongzhi Liang; Li Dang; Ruixue Ding; Shubin Liu 001; Zhangming Zhu (Microelectron. J., 2025)

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu 001; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong 002; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE J. Solid State Circuits, 2025)

A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer. - Linwei Wang; Rong Zhou; Jianhang Yang; Zhen Li; Zhicheng Dong 002; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 36.8-μW 66 nV/√Hz 85.7 dB-System-SNDR Reconfigurable Single-Channel ExG Acquisition System for Bio-Sensor Modules. - Yuke Shen; Jiacheng Liu; Kui Wen; Yanbo Zhang; Yi Shen 007; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs. - Yixiao Luo; Hongzhi Liang; Zeyu Peng; Yukui Yu; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A -79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application. - Jianhang Yang; Rong Zhou; Xianlong Xiong; Linwei Wang; Hongjian Lan; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration. - Feng Bu; Ruixue Ding; Depeng Sun; Ge Wang; Yuan Gao 011; Rong Zhou; Xiaoteng Zhao; Lisheng Chen; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC. - Le Chen; Yue Cao; Lin Ling; Shubin Liu 001; Haolin Han (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme. - Junyan Hao; Minglei Zhang; Zijian Liu; Yanbo Zhang; Shubin Liu 001; Zhangming Zhu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)

A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth. - Junyan Bi; Hao Xu 005; Tenghao Zou; Yaxin Zeng; Yechen Tian; Weitao He; Junjie Gu; Ziyang Jiao; Shubin Liu 001; Zhangming Zhu; Na Yan 004 (IEEE J. Solid State Circuits, 2025)

An 8-bit 5-GS/s Single-Channel Hybrid ADC With a λ/4 Transmission Line Based Time Quantizer. - Hongzhi Liang; Yi Shen 007; Jun Chang; Shubin Liu 001; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Low-Noise Class-F23 VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications. - Yuan Gao 011; Depeng Sun; Chao Gu; Feng Bu; Bowen Wang 001; Rong Zhou; Zhicheng Dong 002; Xiaoteng Zhao; Tao Zhang 086; Ruixue Ding; Shubin Liu 001; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)