A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s. - Kejun Wu; Yangchen Xie; Shubo Tao; Zhong Zhang 002; Ning Ning 002; Jing Li 022; Qi Yu 002 (Microelectron. J., 2023)