High Speed Parallel Architecture for Cyclic Convolution Based on FNT. - Jian Zhang; Shuguo Li (ISVLSI, 2009)

Area-delay efficient parallel architecture for Fermat number transform. - Shuguo Li; Jian Zhang (IEICE Electron. Express, 2009)

Efficient FPGA implementation of sharp FIR filters using the FRM technique. - Shuguo Li; Jian Zhang (IEICE Electron. Express, 2009)

Data-recovery algorithm and circuit for cyclic convolution based on FNT. - Jian Zhang; Shuguo Li (IEICE Electron. Express, 2009)

Random numbers from an integrated CMOS double-scroll. - Shuguo Li; Fuqiang Cao (IEICE Electron. Express, 2010)

CSA-based design of feedforward scalable montgomery modular multiplier. - Tao Wu; Shuguo Li; Litian Liu (ISSPIT, 2011)

Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications. - Tao Wu; Shuguo Li; Litian Liu (Integr., 2013)

A Digital TRNG Based on Cross Feedback Ring Oscillators. - Lijuan Li 002; Shuguo Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Fast RSA decryption through high-radix scalable Montgomery modular multipliers. - Tao Wu; Shuguo Li; Litian Liu (Sci. China Inf. Sci., 2015)

A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(p). - Xiang Feng; Shuguo Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

The ASIC Implementation of SM3 Hash Algorithm for High Throughput. - Xiaojing Du; Shuguo Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A High-Speed Digital True Random Number Generator Based on Cross Ring Oscillator. - Yuanhao Wang 003; Shuguo Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m). - Lijuan Li 002; Shuguo Li (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition. - Jinnan Ding; Shuguo Li (FPL, 2017)

Broken-Karatsuba multiplication and its application to Montgomery modular multiplication. - Jinnan Ding; Shuguo Li (FPL, 2017)

High throughput AES encryption/decryption with efficient reordering and merging techniques. - Lijuan Li 002; Shuguo Li (FPL, 2017)

Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs. - Yifeng Mo; Shuguo Li (FPL, 2017)

A 3DES implementation especially for CBC feedback loop mode. - Yongcheng He; Shuguo Li (ISCAS, 2017)

Fast inversion in GF(2m) with polynomial basis using optimal addition chains. - Lijuan Li 002; Shuguo Li (ISCAS, 2017)

A new digital true random number generator based on delay chain feedback loop. - Xufan Wu; Shuguo Li (ISCAS, 2017)

Design of a fast number theoretical transform engine for fully homomorphic encryption. - Xiang Feng; Shuguo Li (ISCE, 2017)

A design for high speed leading-zero counter. - Jia Miao; Shuguo Li (ISCE, 2017)

A Reconfigurable High-Speed ECC Processor Over NIST Primes. - Jinnan Ding; Shuguo Li (TrustCom/BigDataSE/ICESS, 2017)

A High-Speed and SPA-Resistant Implementation of ECC Point Multiplication Over GF(p). - Xiang Feng; Shuguo Li (TrustCom/BigDataSE/ICESS, 2017)

Base Extent Optimization for RNS Montgomery Algorithm. - Yifeng Mo; Shuguo Li (TrustCom/BigDataSE/ICESS, 2017)

Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. - Xiang Feng; Shuguo Li (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Lazy Reduction and Multi-Precision Division Based on Modular Reductions. - Shuguo Li; Zhen Gu (APCCAS, 2018)

An Implementation of Karatsuba-based Montgomery Modular Multiplication with Only Half-size Additions. - Zhen Gu; Shuguo Li (ISCAS, 2018)

A Modular Multiplier Implemented With Truncated Multiplication. - Jinnan Ding; Shuguo Li (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Improved Algorithms and Implementations for Integer to τ NAF Conversion for Koblitz Curves. - Lijuan Li 002; Shuguo Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

High-Performance Pipelined Architecture of Point Multiplication on Koblitz Curves. - Lijuan Li 002; Shuguo Li (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Design and Implementation of Montgomery Modular Multiplier. - Ruirui Liu; Shuguo Li (ISCAS, 2019)

A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets. - Zhen Gu; Shuguo Li (IEEE Trans. Computers, 2019)

High-Speed ECC Processor Over NIST Prime Fields Applied With Toom-Cook Multiplication. - Jinnan Ding; Shuguo Li; Zhen Gu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Accelerating an FHE Integer Multiplier Using Negative Wrapped Convolution and Ping-Pong FFT. - Xiang Feng; Shuguo Li (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Division-Free Toom-Cook Multiplication-Based Montgomery Modular Multiplication. - Zhen Gu; Shuguo Li (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication. - Zhen Gu; Shuguo Li (ARITH, 2020)

A Binary Counter Based on Stacking and Sorting. - Yating Du; Shuguo Li (ICCE, 2020)

A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area. - Qing Liao 005; Shuguo Li (ICDSP, 2020)

A High-Throughput Hardware Implementation of SHA-256 Algorithm. - Yimeng Chen; Shuguo Li (ISCAS, 2020)

A Low-Latency and Low-Cost Montgomery Modular Multiplier Based on NLP Multiplication. - Jinnan Ding; Shuguo Li (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane Stockham NTT Algorithm. - Xiang Feng; Shuguo Li; Sufen Xu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

An Efficient Implementation of the NewHope Key Exchange on FPGAs. - Yufei Xing; Shuguo Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT. - Shuguo Li; Wenbo Guo 009 (ISCAS, 2021)

A Multibit Left-Shift Modular Inverse Hardware Algorithm and its Implementation. - Jinpeng Lu; Shuguo Li (ISCAS, 2021)

High-Performance Constant-Time Discrete Gaussian Sampling. - Liang Kong 003; Shuguo Li; Ruirui Liu (IEEE Trans. Computers, 2021)

A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA. - Yufei Xing; Shuguo Li (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Fast Binary Counters and Compressors Generated by Sorting Network. - Wenbo Guo 009; Shuguo Li (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers. - Tianqi Kong; Shuguo Li (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Optimized Interpolation of Four-Term Karatsuba Multiplication and a Method of Avoiding Negative Multiplicands. - Zhen Gu; Shuguo Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Efficient Implementation of KYBER. - Wenbo Guo 009; Shuguo Li; Liang Kong 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access Pattern. - Wenbo Guo 009; Shuguo Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber. - Wenbo Guo 009; Shuguo Li (IEEE Trans. Computers, 2024)

Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus. - Tianqi Kong; Shuguo Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Design an Efficient FPGA-Based Accelerator for Leveled BFV Homomorphic Encryption. - Liang Kong 003; Guojie Qin; Shuguo Li (IEEE Trans. Circuits Syst. II Express Briefs, 2024)