Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. - Kentaro Honda; Kousuke Miyaji; Shuhei Tanakamaru; Shinji Miyano; Ken Takeuchi (CICC, 2010)

95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. - Shuhei Tanakamaru; Chinglin Hung; Atsushi Esumi; Mitsuyoshi Ito; Kai Li; Ken Takeuchi (ISSCC, 2011)

Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. - Kousuke Miyaji; Shuhei Tanakamaru; Kentaro Honda; Shinji Miyano; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

A 0.5 V Operation V TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems. - Shuhei Tanakamaru; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. - Shuhei Tanakamaru; Yuki Yanagihara; Ken Takeuchi (ISSCC, 2012)

Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs). - Ken Takeuchi; Teruyoshi Hatanaka; Shuhei Tanakamaru (IEICE Electron. Express, 2012)

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. - Kousuke Miyaji; Kentaro Honda; Shuhei Tanakamaru; Shinji Miyano; Ken Takeuchi (IEICE Trans. Electron., 2012)

Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. - Shuhei Tanakamaru; Chinglin Hung; Ken Takeuchi (IEEE J. Solid State Circuits, 2012)

Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. - Shuhei Tanakamaru; Yuki Yanagihara; Ken Takeuchi (ASP-DAC, 2013)

Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (ISSCC, 2013)

Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). - Shuhei Tanakamaru; Yuki Yanagihara; Ken Takeuchi (IEEE J. Solid State Circuits, 2013)

19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. - Shuhei Tanakamaru; Hiroki Yamazawa; Tsukasa Tokutomi; Sheyang Ning; Ken Takeuchi (ISSCC, 2014)

Application-aware solid-state drives (SSDs) with adaptive coding. - Shuhei Tanakamaru; Yuta Kitamura; Senju Yamazaki; Tsukasa Tokutomi; Ken Takeuchi (VLSIC, 2014)

NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. - Tsukasa Tokutomi; Masafumi Doi; Shogo Hachiya; Atsuro Kobayashi; Shuhei Tanakamaru; Ken Takeuchi (ISSCC, 2015)

Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. - Shuhei Tanakamaru; Hiroki Yamazawa; Ken Takeuchi (VLSIC, 2015)

Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. - Senju Yamazaki; Shuhei Tanakamaru; Sakuya Suzuki; Tomoko Ogura Iwasaki; Shogo Hachiya; Ken Takeuchi (VLSIC, 2015)

A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (IEICE Trans. Electron., 2015)

Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). - Shuhei Tanakamaru; Yuta Kitamura; Senju Yamazaki; Tsukasa Tokutomi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. - Shuhei Tanakamaru; Hiroki Yamazawa; Tsukasa Tokutomi; Sheyang Ning; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. - Hirofumi Takishita; Shuhei Tanakamaru; Sheyang Ning; Ken Takeuchi (IEICE Trans. Electron., 2016)

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. - Sheyang Ning; Tomoko Ogura Iwasaki; Shuhei Tanakamaru; Darlene Viviani; Henry Huang; Monte Manning; Thomas Rueckes; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. - Shuhei Tanakamaru; Shogo Hosaka; Koh Johguchi; Hirofumi Takishita; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2016)