Interconnection network for bucket collection on relational algebra machine GRACE. - Shuichi Sakai; Masaru Kitsuregawa; Hidehiko Tanaka; Tohru Moto-Oka (Syst. Comput. Jpn., 1985)

Interconnection networks for bucket distribution on relational algebra machine GRACE. - Shuichi Sakai; Masaru Kitsuregawa; Hidehiko Tanaka; Tohru Moto-Oka (Syst. Comput. Jpn., 1986)

An Architectural Disgn of a Highly Parallel Dataflow Machine. - Yoshinori Yamaguchi; Shuichi Sakai; Kei Hiraki; Yuetsu Kodama (IFIP Congress, 1989)

An Architecture of a Dataflow Single Chip Processor. - Shuichi Sakai; Yoshinori Yamaguchi; Kei Hiraki; Yuetsu Kodama; Toshitsugu Yuba (ISCA, 1989)

Dataflow computer development in Japan. - Toshitsugu Yuba; Toshio Shimada; Yoshinori Yamaguchi; Kei Hiraki; Shuichi Sakai (ICS, 1990)

Design and Implementation of a Versatile Interconnection Network in the EM-4. - Shuichi Sakai; Yuetsu Kodama; Yoshinori Yamaguchi (ICPP (1), 1991)

Prototype Implementation of a Highly Parallel Dataflow Machine EM-4. - Shuichi Sakai; Yuetsu Kodama; Yoshinori Yamaguchi (IPPS, 1991)

Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. - Kenji Toda; Kenji Nishida; Yoshinobu Uchibori; Shuichi Sakai; Toshio Shimada (IPPS, 1991)

Load balancing by function distribution on the EM-4 prototype. - Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi (SC, 1991)

Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem. - Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi (FGCS, 1992)

Thread-based Programming for the EM-4 Hybrid Dataflow Machine. - Mitsuhisa Sato; Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi; Yasuhito Koumura (ISCA, 1992)

A priority forwarding scheme for real-time multistage interconnection networks. - Kenji Toda; Kenji Nishida; Shuichi Sakai; Toshio Shimada (RTSS, 1992)

A prototype of a highly parallel dataflow machine EM-4 and its preliminary evaluation. - Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi (Future Gener. Comput. Syst., 1992)

Methodologies in development and testing of the dataflow machine EM-4. - Kazuaki Okamoto; Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi (Parallel Comput., 1992)

EMC-Y: Parallel Processing Element Optimizing Communication and Computation. - Yuetsu Kodama; Yasuhito Koumura; Mitsuhisa Sato; Hirohumi Sakane; Shuichi Sakai; Yoshinori Yamaguchi (International Conference on Supercomputing, 1993)

Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation. - Shuichi Sakai; Kazuaki Okamoto; Hiroshi Matsuoka; Hideo Hirono; Yuetsu Kodama; Mitsuhisa Sato (International Conference on Supercomputing, 1993)

RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. - Shuichi Sakai; Hiroshi Matsuoka; Yuetsu Kodama; Mitsuhisa Sato; Andrew Shaw; Hideo Hirono; Kazuaki Okamoto; Takashi Yokota (SPDP, 1993)

Design and Implementation of a Circular Omega Network in the EM-4. - Shuichi Sakai; Yuetsu Kodama; Yoshinori Yamaguchi (Parallel Comput., 1993)

Evaluation of parallel execution performance by highly parallel computer EM-4. - Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi (Syst. Comput. Jpn., 1993)

Overview of RWC Massively Parallel Computer Project. - Shuichi Sakai (HPDC, 1994)

EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor. - Mitsuhisa Sato; Yuetsu Kodama; Shuichi Sakai; Yoshinori Yamaguchi (IFIP PACT, 1994)

Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4. - Mitsuhisa Sato; Yuetsu Kodama; Yoshinori Yamaguchi; Shuichi Sakai (IPPS, 1994)

Message-based efficient remote memory access on a highly parallel computer EM-X. - Yuetsu Kodama; Hirofumi Sakane; Mitsuhisa Sato; Shuichi Sakai; Yoshinori Yamaguchi (ISPAN, 1994)

Nonnumeric search results on the EM-4 distributed-memory multiprocessor. - Andrew Sohn; Mitsuhisa Sato; Shuichi Sakai; Yuetsu Kodama; Yoshinori Yamaguchi (SC, 1994)

Parallel bidirectional heuristic search on the EM-4 multiprocessor. - Andrew Sohn; Mitsuhisa Sato; Shuichi Sakai; Yuetsu Kodama; Yoshinori Yamaguchi (SPDP, 1994)

Programming with Distributed Data Structure for EM-X Multiprocessor. - Mitsuhisa Sato; Yuetsu Kodama; Hirofumi Sakane; Yoshinori Yamaguchi; Shuichi Sakai (Theory and Practice of Parallel Programming, 1994)

A prototype router for the massively parallel computer RWC-1. - Takashi Yokota; Hiroshi Matsuoka; Kazuaki Okamoto; Hideo Hirono; Atsushi Hori; Shuichi Sakai (ICCD, 1995)

A Macrotask-level Unlimited Speculative Execution on Multiprocessors. - Hayato Yamana; Mitsuhisa Sato; Yuetsu Kodama; Hirofumi Sakane; Shuichi Sakai; Yoshinori Yamaguchi (International Conference on Supercomputing, 1995)

The EM-X Parallel Computer: Architecture and Basic Performance. - Yuetsu Kodama; Hirohumi Sakane; Mitsuhisa Sato; Hayato Yamana; Shuichi Sakai; Yoshinori Yamaguchi (ISCA, 1995)

Time Space Sharing Scheduling and Architectural Support. - Atsushi Hori; Takashi Yokota; Yutaka Ishikawa; Shuichi Sakai; Hiroki Konaka; Munenori Maeda; Takashi Tomokiyo; Jörg Nolte; Hiroshi Matsuoka; Kazuaki Okamoto; Hideo Hirono (JSSPP, 1995)

Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. - Shuichi Sakai; Yuetsu Kodama; Mitsuhisa Sato; Andrew Shaw; Hiroshi Matsuoka; Hideo Hirono; Kazuaki Okamoto; Takashi Yokota (Parallel Comput., 1995)

Multithread execution mechanisms on RICA-1 for massively parallel computation. - Kazuaki Okamoto; Shuichi Sakai; Hiroshi Matsuoka; Takashi Yokota; Hideo Hirono (IEEE PACT, 1996)

Identifying the capability of overlapping computation with communication. - Andrew Sohn; Jui Ku; Yuetsu Kodama; Mitsuhisa Sato; Hirofumi Sakane; Hayato Yamana; Shuichi Sakai; Yoshinori Yamaguchi (IEEE PACT, 1996)

Parallel Execution of Radix Sort Program Using Fine-Grain Communication. - Yuetsu Kodama; Hirofumi Sakane; Hanpei Koike; Mitsuhisa Sato; Shuichi Sakai; Yoshinori Yamaguchi (IEEE PACT, 1997)

Virtual control channel and its application to the massively parallel computer RWC-1. - Takashi Yokota; Hiroshi Matsuoka; Kazuaki Okamoto; Hideo Hirono; Shuichi Sakai (HiPC, 1997)

Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation. - Mitsuhisa Sato; Yuetsu Kodama; Hirofumi Sakane; Hayato Yamana; Shuichi Sakai; Yoshinori Yamaguchi (IPPS, 1997)

Fine-Grain Multithreading with the EM-X Multiprocessor. - Andrew Sohn; Yuetsu Kodama; Jui Ku; Mitsuhisa Sato; Hirofumi Sakane; Hayato Yamana; Shuichi Sakai; Yoshinori Yamaguchi (SPAA, 1997)

Inter-procedural Analysis for Parallelization of Java Programs. - Antonio Magnaghi; Shuichi Sakai; Hidehiko Tanaka (ACPC, 1999)

Relating Graphical Features with Concept Classes for Automatic News Video Indexing. - Ichiro Ide; Reiko Hamada; Shuichi Sakai; Hidehiko Tanaka (Intelligent Information Integration, 1999)

Associating video with related documents. - Reiko Hamada; Ichiro Ide; Shuichi Sakai; Hidehiko Tanaka (ACM Multimedia (2), 1999)

Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams. - Masaaki Honda; Takeo Igarashi; Hidehiko Tanaka; Shuichi Sakai (ACM Symposium on User Interface Software and Technology, 1999)

Structural analysis of cooking preparation steps in Japanese. - Reiko Hamada; Ichiro Ide; Shuichi Sakai; Hidehiko Tanaka (IRAL, 2000)

Associating cooking video with related textbook. - Reiko Hamada; Ichiro Ide; Shuichi Sakai (ACM Multimedia Workshops, 2000)

Scene identification in news video by character region segmentation. - Ichiro Ide; Reiko Hamada; Shuichi Sakai; Hidehiko Tanaka (ACM Multimedia Workshops, 2000)

Improving Conditional Branch Prediction on Speculative Multithreading Architectures. - Chitaka Iwama; Niko Demus Barli; Shuichi Sakai; Hidehiko Tanaka (Euro-Par, 2001)

An attribute based news video indexing. - Ichiro Ide; Reiko Hamada; Shuichi Sakai; Hidehiko Tanaka (ACM Multimedia Workshops, 2001)

An object detection method for describing soccer games from video. - Okihisa Utsumi; Koichi Miura; Ichiro Ide; Shuichi Sakai; Hidehiko Tanaka (ICME (1), 2002)

CMP on SoC: Architect's View. - Shuichi Sakai (ISSS, 2002)

Associating Cooking Video Segments with Preparation Steps. - Koichi Miura; Reiko Hamada; Ichiro Ide; Shuichi Sakai; Hidehiko Tanaka (CIVR, 2003)

Compiler-Assisted Thread Level Control Speculation. - Hideyuki Miura; Luong Dinh Hung; Chitaka Iwama; Daisuke Tashiro; Niko Demus Barli; Shuichi Sakai; Hidehiko Tanaka (Euro-Par, 2003)

Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. - Yoshimitsu Yanagawa; Luong Dinh Hung; Chitaka Iwama; Niko Demus Barli; Shuichi Sakai; Hidehiko Tanaka (HiPC, 2003)

A note on greedy algorithms for the maximum weighted independent set problem. - Shuichi Sakai; Mitsunori Togasaki; Koichi Yamazaki (Discret. Appl. Math., 2003)

Compilation of dictionaries for semantic attribute analysis of television news captions. - Ichiro Ide; Reiko Hamada; Shuichi Sakai; Hidehiko Tanaka (Syst. Comput. Jpn., 2003)

Multimedia Integration for Cooking Video Indexing. - Reiko Hamada; Koichi Miura; Ichiro Ide; Shin'ichi Satoh 001; Shuichi Sakai; Hidehiko Tanaka (PCM (2), 2004)

Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. - Luong Dinh Hung; Masahiro Goshima; Shuichi Sakai (ICCD, 2005)

Cooking navi: assistant for daily cooking in kitchen. - Reiko Hamada; Jun Okabe; Ichiro Ide; Shin'ichi Satoh 001; Shuichi Sakai; Hidehiko Tanaka (ACM Multimedia, 2005)

Associating semantically structured cooking videos with their preparation steps. - Koichi Miura; Motomu Takano; Reiko Hamada; Ichiro Ide; Shuichi Sakai; Hidehiko Tanaka (Syst. Comput. Jpn., 2005)

SEVA: A Soft-Error- and Variation-Aware Cache Architecture. - Luong Dinh Hung; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

Base Address Recognition with Data Flow Tracking for Injection Attack Detection. - Satoshi Katsunuma; Hiroyuki Kurita; Ryota Shioya; Kazuto Shimizu; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

Bus Serialization for Reducing Power Consumption. - Naoya Hatta; Niko Demus Barli; Chitaka Iwama; Luong Dinh Hung; Daisuke Tashiro; Shuichi Sakai; Hidehiko Tanaka (Inf. Media Technol., 2006)

Dynamic Estimation of Task Level Parallelism with Operating System Support. - Luong Dinh Hung; Shuichi Sakai (Inf. Media Technol., 2006)

Utilization of SECDED for soft error and variation-induced defect tolerance in caches. - Luong Dinh Hung; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (DATE, 2007)

Musical part separation based on perceptual hierarchy. - Tomoyoshi Kinoshita; Ibuki Handa; Makoto Muto; Shuichi Sakai; Hidehiko Tanaka (Syst. Comput. Jpn., 2007)

Preventing timing errors on register writes: mechanisms of detections and recoveries. - Hidetsugu Irie; Ken Sugimoto; Masahiro Goshima; Shuichi Sakai (SIGARCH Comput. Archit. News, 2007)

Ultra Dependable Processor. - Shuichi Sakai; Masahiro Goshima; Hidetsugu Irie (IEICE Trans. Electron., 2008)

Dependable VLSI: device, design and architecture: how should they cooperate? - Shuichi Sakai; Hidetoshi Onodera; Hiroto Yasuura; James C. Hoe (ASP-DAC, 2009)

String-Wise Information Flow Tracking against Script Injection Attacks. - Kunbo Li; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (PRDC, 2009)

Register Cache System Not for Latency Reduction Purpose. - Ryota Shioya; Kazuo Horio; Masahiro Goshima; Shuichi Sakai (MICRO, 2010)

Low-Overhead Architecture for Security Tag. - Ryota Shioya; Daewung Kim; Kazuo Horio; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2011)

Register Indirect Jump Target Forwarding. - Ryota Shioya; Naruki Kurata; Takashi Toyoshima; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2013)

A cloud architecture for protecting guest's information from malicious operators with memory management. - Koki Murakami; Tsuyoshi Yamada; Rie Shigetomi Yamaguchi; Masahiro Goshima; Shuichi Sakai (CODASPY, 2014)

Address Order Violation Detection with Parallel Counting Bloom Filters. - Naruki Kurata; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2015)

"Stubborn" strategy to mitigate remaining cache misses. - Hayato Nomura; Hiroyuki Katchi; Hidetsugu Irie; Shuichi Sakai (ICCD, 2016)

High-Accuracy Joint Position Estimation and Posture Detection System for Driving. - Takahiro Yamada; Hidetsugu Irie; Shuichi Sakai (MobiQuitous (Adjunct Proceedings), 2016)

An Inductive Method to Select Simulation Points. - Minseong Choi; Takashi Fukuda; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2016)

Accelerating Integrity Verification on Secure Processors by Promissory Hash. - Mizuki Miyanaga; Hidetsugu Irie; Shuichi Sakai (PRDC, 2017)

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2017)

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2017)

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. - Junichiro Kadomoto; Toru Koizumi 001; Akifumi Fukuda; Reoma Matsuo; Susumu Mashimo; Akifumi Fujita; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPT, 2018)

Reduction of Instruction Increase Overhead by STRAIGHT Compiler. - Toru Koizumi 001; Satoshi Nakae; Akifumi Fukuda; Hidetsugu Irie; Shuichi Sakai (CANDAR Workshops, 2018)

Estimating driver's readiness by understanding driving posture. - Takahiro Yamada; Hidetsugu Irie; Masahiro Kunitake; Eiji Nagano; Shuichi Sakai (ICCE, 2018)

STRAIGHT: Hazardless Processor Architecture Without Register Renaming. - Hidetsugu Irie; Toru Koizumi 001; Akifumi Fukuda; Seiya Akaki; Satoshi Nakae; Yutaro Bessho; Ryota Shioya; Takahiro Notsu; Katsuhiro Yoda; Teruo Ishihara; Shuichi Sakai (MICRO, 2018)

Bank-Aware Instruction Scheduler for a Multibanked Register File. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (J. Inf. Process., 2018)

WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2019)

An Inductively Coupled Wireless Bus for Chiplet-Based Systems. - Junichiro Kadomoto; Satoshi Mitsuno; Hidetsugu Irie; Shuichi Sakai (ASP-DAC, 2020)

A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (AsianCHI@CHI, 2020)

A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (COOL CHIPS, 2020)

A High-Performance Out-of-Order Soft Processor Without Register Renaming. - Satoshi Mitsuno; Junichiro Kadomoto; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPL, 2020)

Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2020)

Compiling and Optimizing Real-world Programs for STRAIGHT ISA. - Toru Koizumi 001; Shu Sugita; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. - Tomoki Nakamura; Kazutaka Tomida; Shouta Kouno; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Multiport Register File Design for High-Performance Embedded Cores. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MCSoC, 2021)

Toward Wirelessly Cooperated Shape-Changing Computing Particles. - Junichiro Kadomoto; Takuya Sasatani; Koya Narumi; Naoto Usami; Hidetsugu Irie; Shuichi Sakai; Yoshihiro Kawahara (IEEE Pervasive Comput., 2021)

Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ASP-DAC, 2022)

T-SKID: Predicting When to Prefetch Separately from Address Prediction. - Toru Koizumi 001; Tomoki Nakamura; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (DATE, 2022)

Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MCSoC, 2022)

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. - Shu Sugita; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (CC, 2023)

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. - Taichi Amano; Junichiro Kadomoto; Satoshi Mitsuno; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (ISCAS, 2023)

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. - Toru Koizumi 001; Ryota Shioya; Shu Sugita; Taichi Amano; Yuya Degawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MICRO, 2023)

Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. - Kenta Higuchi; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (SenSys, 2023)

Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (SenSys, 2023)

A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. - Yusuke Izawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (SPLASH Companion, 2023)

iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. - Takashi Murayama; Shu Sugita; Hiroyuki Saegusa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (UIST (Adjunct Volume), 2023)

Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. - Shun Nagasaki; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEEE Des. Test, 2023)

A Principal Factor of Performance in Decoupled Front-End. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEICE Trans. Inf. Syst., 2023)

FPGA-based Garbling Accelerator with Parallel Pipeline Processing. - Rin Oishi; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEICE Trans. Inf. Syst., 2023)

A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (APCCAS, 2024)

Designing a Reactive Programming Language for Shape-Adaptive Computers. - Yusuke Izawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (APSEC, 2024)

Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. - Shun Nagasaki; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (CF, 2024)

CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. - Masato Goto; Ibuki Sugiyama; Kenta Higuchi; Toshiki Goto; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (CHI Extended Abstracts, 2024)

Branch Divergence-Aware Flexible Approximating Technique on GPUs. - Reoma Matsuo; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (COOL CHIPS, 2024)

DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication. - Shoi To; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (UIST (Adjunct Volume), 2024)

Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements. - Yuya Degawa; Shota Suzuki; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEEE Comput. Archit. Lett., 2024)

TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Comput. Archit. Lett., 2024)

Biotite: A High-Performance Static Binary Translator using Source-Level Information. - Changbin Chen; Shu Sugita; Yotaro Nada; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (CC, 2025)

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEICE Trans. Inf. Syst., 2025)

Flexible Approximate Computing for Mitigating Branch Divergence in GPUs. - Reoma Matsuo; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Micro, 2025)