570-ps 13-mW Josephson 1-kbit NDRO RAM. - Shuichi Nagasawa; Yoshifusa Wada; Mutsuo Hidaka; Hisanao Tsuge; Iichiro Ishida; Shuichi Tahara (IEEE J. Solid State Circuits, 1989)

Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. - Tsuneo Inaba; Kenji Tsuchida; Tadahiko Sugibayashi; Shuichi Tahara; Hiroaki Yoda (CICC, 2003)

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. - Yoshihisa Iwata; Kenji Tsuchida; Tsuneo Inaba; Yui Shimizu; R. Takizawa; Yoshihiro Ueda; Tadahiko Sugibayashi; Yoshiaki Asao; Takeshi Kajiyama; Keiji Hosotani; Sumio Ikegawa; Tadashi Kai; et al. (ISSCC, 2006)

TD: Emerging Devices Devices and Circuits. - Eugenio Cantatore; Shuichi Tahara (ISSCC, 2007)

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. - Takeshi Honda; Noboru Sakimura; Tadahiko Sugibayashi; Naoki Kasai; Hiromitsu Hada; Shuichi Tahara (IEICE Trans. Electron., 2007)

MRAM Applications Using Unlimited Write Endurance. - Tadahiko Sugibayashi; Takeshi Honda; Noboru Sakimura; Shuichi Tahara; Naoki Kasai (IEICE Trans. Electron., 2007)

MRAM Cell Technology for Over 500-MHz SoC. - Noboru Sakimura; Tadahiko Sugibayashi; Takeshi Honda; Hiroaki Honjo; Shinsaku Saito; Tetsuhiro Suzuki; Nobuyuki Ishiwata; Shuichi Tahara (IEEE J. Solid State Circuits, 2007)

A 16-Mb Toggle MRAM With Burst Modes. - Tadahiko Sugibayashi; Noboru Sakimura; Takeshi Honda; Kiyokazu Nagahara; Kiyotaka Tsuji; Hideaki Numata; Sadahiko Miura; Ken-ichi Shimura; Yuko Kato; Shinsaku Saito; Yoshiyuki Fukumoto; Hiroaki Honjo; et al. (IEEE J. Solid State Circuits, 2007)