A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm. - Shuilong Huang; Zhihua Wang; Huainan Ma (APCCAS, 2006)

Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. - Shuilong Huang; Huainan Ma; Zhihua Wang (DATE, 2007)

A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm. - Shuilong Huang; Zhihua Wang (ISCAS, 2007)

System Design Considerations of Highly-Integrated SigmaDelta fractional-n Frequency synthesizer. - Shuilong Huang; Zhihua Wang 001 (J. Circuits Syst. Comput., 2008)

11b 60 MHz pipelined ADC with inverter-based class AB amplifier in 28 nm CMOS technology. - Zihui Wei; Yanbin Xiao; Shuilong Huang (IEICE Electron. Express, 2017)

A 16.5-μW 73.7-dB-SNDR Second-Order Fully Passive Noise-Shaping SAR ADC With a Hybrid Switching Procedure. - Zheng Li; Yating Yang; Mingyang Liu; Wei Liu; Ying Hou; Zihui Wei; Xiaosong Wang 002; Zhenming Li; Shuilong Huang; Yu Liu 030 (IEEE Access, 2023)