A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current. - Katsuro Sasaki; Koichiro Ishibashi; Katsuhiro Shimohigashi; Toshiaki Yamanaka; Nobuyuki Moriwake; Shigeru Honjo; Shuji Ikeda; Atsuyoshi Koike; Satoshi Meguro; Osamu Minato (IEEE J. Solid State Circuits, 1990)

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. - Koichiro Ishibashi; Kunihiro Komiyaji; Sadayuki Morita; Toshiro Aoto; Shuji Ikeda; Kyoichiro Asayama; Atsuyosi Koike; Toshiaki Yamanaka; Naotaka Hashimoto; Haruhito Iida; Fumio Kojima; Koichi Motohashi; et al. (IEEE J. Solid State Circuits, 1994)

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. - Hiroyuki Mizuno; Koichiro Ishibashi; Takanori Shimura; Toshihiro Hattori; Susumu Narita; Kenji Shiozawa; Shuji Ikeda; Kunio Uchiyama (IEEE J. Solid State Circuits, 1999)

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. - Kenichi Osada; Jinuk Luke Shin; Masood Khan; Yude Liou; Karl Wang; Kenichi Shoji; Kenichi Kuroda; Shuji Ikeda; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2001)