A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks. - Zupei Gu; Shukao Dou; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEEE Access, 2024)

An energy-efficient readout method based on weight-flip-store coding and quantization cycle skipping technology for computing in memory. - Shukao Dou; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2025)

A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation. - Shukao Dou; Zupei Gu; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2025)