An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (AICCSA, 2006)

Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini; J. M. Pierre Langlois (SoCC, 2006)

FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (ASAP, 2007)

Optimised realisations of large integer multipliers and squarers using embedded blocks. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (IET Comput. Digit. Tech., 2007)

Two level decomposition based matrix multiplication for FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (ICECS, 2009)

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (Int. J. Reconfigurable Comput., 2009)

FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (J. Signal Process. Syst., 2010)

Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (ICECS, 2011)

Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (IPDPS Workshops, 2011)

A Highly Sensitive and Selective Competition Assay for the Detection of Cysteine Using Mercury-Specific DNA, Hg2+ and Sybr Green I. - Hui Xu; Shuli Gao; Quanwen Liu; Dun Pan; Lihua Wang; Shuzhen Ren; Min Ding; Jingwen Chen; Gang Liu (Sensors, 2011)

An improved BCD adder using 6-LUT FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (NEWCAS, 2012)

Asymmetric large size multipliers with optimised FPGA resource utilisation. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini; J. M. Pierre Langlois (IET Comput. Digit. Tech., 2012)

FPGA implementation of multiple Pursuit-Evasion games with decentralized Learning Automata. - Shuli Gao; Sidney N. Givigi; Alain J. G. Beaulieu (SysCon, 2014)

Factors affecting the performance of knowledge collaboration in virtual team based on capital appreciation. - Shuli Gao; Yanli Guo; Jianbin Chen; Lin Li (Inf. Technol. Manag., 2016)

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. - Shuli Gao; Dhamin Al-Khalili; J. M. Pierre Langlois; Noureddine Chabini (CCECE, 2017)

Random channel generator of the integrated power line communication and visible light communication. - Shuli Gao; Jian Zhang; Jian Song 004; Hui Yang 007; Xi Chu (ISPLC, 2017)

Efficient Realization of BCD Multipliers Using FPGAs. - Shuli Gao; Dhamin Al-Khalili; J. M. Pierre Langlois; Noureddine Chabini (Int. J. Reconfigurable Comput., 2017)

Step-Video-T2V Technical Report: The Practice, Challenges, and Future of Video Foundation Model. - Guoqing Ma; Haoyang Huang; Kun Yan; Liangyu Chen 002; Nan Duan; Shengming Yin; Changyi Wan; Ranchen Ming; Xiaoniu Song; Xing Chen; Yu Zhou 010; Deshan Sun; et al. (CoRR, 2025)

Step-Audio: Unified Understanding and Generation in Intelligent Speech Interaction. - Ailin Huang; Boyong Wu; Bruce Wang; Chao Yan; Chen Hu; Chengli Feng; Fei Tian; Feiyu Shen; Jingbei Li; Mingrui Chen; Peng Liu; Ruihang Miao; et al. (CoRR, 2025)

Step-Audio 2 Technical Report. - Boyong Wu; Chao Yan; Chen Hu; Cheng Yi; Chengli Feng; Fei Tian; Feiyu Shen; Gang Yu 002; Haoyang Zhang; Jingbei Li; Mingrui Chen; Peng Liu; et al. (CoRR, 2025)