A User-Adaptable VLSI Engine for Artificial Intelligence. - Shumpei Kawasaki; Tohru Nojiri; Kousuke Sakoda (IFIP Congress, 1986)

Microprogrammable Processor for Object-Oriented Architecture. - Tohru Nojiri; Shumpei Kawasaki; Kousuke Sakoda (ISCA, 1986)

A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming. - Shumpei Kawasaki; Mitsuru Watabe; Shigeki Morinaga (IEEE Micro, 1989)

SH3: high code density, low power. - Atsushi Hasegawa; Ikuya Kawasaki; Kouji Yamada; Shinichi Yoshioka; Shumpei Kawasaki; Prasenjit Biswas (IEEE Micro, 1995)

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. - Kesami Hagiwara; Tomoichi Hayashi; Shumpei Kawasaki; Fumio Arakawa; Oleg Endo; Hayato Nomura; Akira Tsukamoto; Duong Nguyen; Binh Nguyen; Anh Tran; Hoan Hyunh; Ikuo Kudoh; et al. (COOL CHIPS, 2018)