Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2016)

Nonlinear delay-table approach for full-chip NBTI degradation prediction. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2016)

Comparative study of path selection and objective function in replacing NBTI mitigation logic. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2017)

Identification and Application of Invariant Critical Paths under NBTI Degradation. - Song Bian 001; Shumpei Morita; Michihiro Shintani; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Scalable Device Array for Statistical Characterization of BTI-Related Parameters. - Hiromitsu Awano; Shumpei Morita; Takashi Sato 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2018)

A study on NBTI-induced delay degradation considering stress frequency dependence. - Zuitoku Shin; Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2018)

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)