A delay test system for high speed logic LSI's. - Kuniaki Kishida; F. Shirotori; Y. Ikemoto; Shun Ishiyama; Terumine Hayashi (DAC, 1986)

Enhanced Delay Test Generator for High-Speed Logic LSIs. - Kazumi Hatayama; Mitsuji Ikeda; Terumine Hayashi; Masahiro Takakura; Kuniaki Kishida; Shun Ishiyama (ITC, 1989)