A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. - Ewout Martens; Davide Dermit; Mithlesh Shrivas; Shun Nagata; Jan Craninckx (VLSI Circuits, 2021)

A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. - Shun Nagata; Ewout Martens; Adam Cooman; Jan Craninckx (MWSCAS, 2023)

22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. - Ewout Martens; Adam Cooman; Pratap Tumkur Renukaswamy; Shun Nagata; Sehoon Park; Jorge-Luis Lagos 001; Nereo Markulic; Jan Craninckx (ISSCC, 2024)