A fast and memory-efficient diagnostic fault simulation for sequential circuits. - Jer-Min Jou; Shung-Chih Chen (ICCAD, 1994)

A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. - Jer-Min Jou; Shung-Chih Chen; Ren-Der Chen (ISCAS, 1994)

Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. - Jer-Min Jou; Shung-Chih Chen (ISCAS, 1995)

Serial diagnostic fault simulation for synchronous sequential circuits. - Shung-Chih Chen; Jer-Min Jou (Integr., 1997)

Diagnostic fault simulation for synchronous sequential circuits. - Shung-Chih Chen; Jer-Min Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A low-power IP design of Viterbi decoder with dynamic threshold setting. - Yi-Ming Lin; Wan-Ching Liu; Li-Yuan Chang; Chih-Yuan Lien; Pei-Yin Chen; Shung-Chih Chen (ISCAS, 2010)