A processor core synthesis system in IP-based SoC design. - Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2005)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. - Shunitsu Kohara; Naoki Tomono; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Kazunori Shimizu; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2008)

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. - Akira Ohchi; Shunitsu Kohara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An integrated optimization framework for reducing the energy consumption of embedded real-time applications. - Hideki Takase; Gang Zeng; Lovic Gauthier; Hirotaka Kawashima; Noritoshi Atsumi; Tomohiro Tatematsu; Yoshitake Kobayashi; Shunitsu Kohara; Takenori Koshiro; Tohru Ishihara; Hiroyuki Tomiyama; Hiroaki Takada (ISLPED, 2011)