The stability of adiabatic reversible logic using asymmetric tank capacitors and its application to SRAM. - Shunji Nakata (IEICE Electron. Express, 2005)

Analysis of the stability of adiabatic reversible logic using the theory of normal modes in coupled oscillators. - Shunji Nakata (IEICE Electron. Express, 2006)

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage. - Shunji Nakata (IEICE Electron. Express, 2006)

Stability of adiabatic reversible charging using 1D-capacitor array between the power supply and ground. - Shunji Nakata (IEICE Electron. Express, 2007)

Stability of adiabatic circuit using asymmetric 1D-capacitor array between the power supply and ground. - Shunji Nakata (IEICE Electron. Express, 2007)

Stability of an adiabatic circuit with inductive load using 1D-capacitor array between the power supply and ground. - Shunji Nakata (IEICE Electron. Express, 2007)

Electrostatic Energy, Potential Energy and Energy Dissipation for a Width-Variable Capacitor Coupled with Mechatronical Potential Energy during Adiabatic Charging. - Shunji Nakata; Yoshitada Katagiri (IEICE Trans. Electron., 2007)

Adiabatic quasi 6T-SRAM with shared writing and reading ports. - Shunji Nakata (IEICE Electron. Express, 2008)

Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage. - Shunji Nakata; Takahito Kusumoto; Masayuki Miyama; Yoshio Matsuda (ISCAS, 2009)

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. - Shunji Nakata; Hirotsugu Suzuki; Ryota Honda; Takahito Kusumoto; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (ISCAS, 2010)

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. - Shunji Nakata; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (IEICE Electron. Express, 2010)

Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system. - Shunji Nakata; Masayuki Miyama; Yoshio Matsuda (IET Circuits Devices Syst., 2010)

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Hiroki Morimura; Yoshio Matsuda (MWSCAS, 2012)

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IET Circuits Devices Syst., 2012)

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Shin'ichiro Mutoh; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. - Shunji Nakata; Hiroshi Makino; Yoshio Matsuda (MWSCAS, 2014)

Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. - Shunji Nakata; Hiroshi Makino; Ryota Honda; Masayuki Miyama; Yoshio Matsuda (J. Circuits Syst. Comput., 2014)

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. - Shunji Nakata; Hiroshi Makino; Junpei Hosokawa; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. - Shunji Nakata; Hiroki Hanazono; Hiroshi Makino; Hiroki Morimura; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor. - Shunji Nakata; Masaki Ono; Masato Sakitani (J. Circuits Syst. Comput., 2017)