Frequency Response Analysis of Latch Utilized in High-Speed Comparator. - Shunsuke Okura; Tetsuro Okura; Kenji Taniguchi 001; Hajime Shibata (ICECS, 2006)

A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC. - Shunsuke Okura; Tetsuro Okura; Indika U. K. Bogoda Appuhamylage; Kenji Taniguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter. - Shunsuke Okura; Tetsuro Okura; Toru Ido; Kenji Taniguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Area-Efficient CMOS Bandgap Reference Utilizing a Switched-Current Technique. - Indika U. K. Bogoda Appuhamylage; Shunsuke Okura; Toru Ido; Kenji Taniguchi 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Frequency Model of a Continuously Driven Clocked CMOS Comparator. - Shunsuke Okura; Hajime Shibata; Tetsuro Okura; Toru Ido; Kenji Taniguchi 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference. - Indika U. K. Bogoda Appuhamylage; Shunsuke Okura; Toru Ido; Kenji Taniguchi 001 (IEICE Trans. Electron., 2011)

A low-power technique for pipelined ADCs with programmable gain amplification. - Tetsuro Okura; Shunsuke Okura; Toshimasa Matsuoka; Kenji Taniguchi 001 (IEICE Electron. Express, 2013)

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. - Kazuhiro Ueda; Fukashi Morishita; Shunsuke Okura; Leona Okamura; Tsutomu Yoshihara; Kazutami Arimoto (IEEE J. Solid State Circuits, 2013)

A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit. - Shunsuke Okura; Osamu Nishikido; Yusuke Sadanaga; Yasuhiro Kosaka; Norihiko Araki; Kazuhiro Ueda; Masanori Tachibana; Fukashi Morishita (VLSIC, 2014)

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. - Shunsuke Okura; Osamu Nishikido; Yusuke Sadanaga; Yasuhiro Kosaka; Norihiko Araki; Kazuhiro Ueda; Fukashi Morishita (IEEE J. Solid State Circuits, 2015)

A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. - Shunsuke Okura; Ryota Ishiki; Masayoshi Shirahata; Takaya Kubota; Mitsuru Shiozaki; Kenichiro Ishikawa; Isao Takayanagi; Takeshi Fujino (ISPACS, 2018)

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process. - Isao Takayanagi; Norio Yoshimura; Kazuya Mori; Shinichiro Matsuo; Shunsuke Tanaka; Hirofumi Abe; Naoto Yasuda; Kenichiro Ishikawa; Shunsuke Okura; Shinji Ohsawa; Toshinori Otaka (Sensors, 2018)

A 120-ke- Full-Well Capacity 160-µV/e- Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor. - Isao Takayanagi; Ken Miyauchi; Shunsuke Okura; Kazuya Mori; Junichi Nakamura; Shigetoshi Sugawa (Sensors, 2019)

Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. - Kota Yoshida; Takaya Kubota; Shunsuke Okura; Mitsuru Shiozaki; Takeshi Fujino (ISCAS, 2020)

Modeling attacks against device authentication using CMOS image sensor PUF. - Hiroshi Yamada; Shunsuke Okura; Masayoshi Shirahata; Takeshi Fujino (IEICE Electron. Express, 2021)

Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. - Kota Yoshida; Mitsuru Shiozaki; Shunsuke Okura; Takaya Kubota; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor. - Shunsuke Okura; Masanori Aoki; Tatsuya Oyama; Masayoshi Shirahata; Takeshi Fujino; Kenichiro Ishikawa; Isao Takayanagi (Sensors, 2021)

Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. - Tatsuya Oyama; Kota Yoshida; Shunsuke Okura; Takeshi Fujino (AsianHOST, 2022)

Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models. - Tatsuya Oyama; Shunsuke Okura; Kota Yoshida; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor. - Ai Otani; Hiroaki Ogawa; Ken Miyauchi; Sangman Han; Hideki Owada; Isao Takayanagi; Shunsuke Okura (Sensors, 2023)

Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. - Tatsuya Oyama; Shunsuke Okura; Kota Yoshida; Takeshi Fujino (Sensors, 2023)

Lightweight Object Detection Model for a CMOS Image Sensor with Binary Feature Extraction. - Keiichiro Kuroda; Yudai Morikaku; Yu Osuka; Ryoya Iegaki; Kota Yoshida; Shunsuke Okura (IEEE SENSORS, 2024)

Defense Method Against Adversarial Example Attacks using Thermal Noise of a CMOS Image Sensor. - Yuki Rogi; Kota Yoshida; Tatsuya Oyama; Takeshi Fujino; Shunsuke Okura (IEEE SENSORS, 2024)

Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. - Tatsuya Oyama; Kota Yoshida; Shunsuke Okura; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

An Area-Efficient Readout Circuit for a High-SNR Triple-Gain LOFIC CMOS Image Sensor. - Ai Otani; Hiroaki Ogawa; Ken Miyauchi; Yuki Morikawa; Hideki Owada; Isao Takayanagi; Shunsuke Okura (ISCAS, 2025)