Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture. - Fahimeh Jafari; Shuo Li 002; Ahmed Hemani (DSD, 2011)

System level synthesis of hardware for DSP applications using pre-characterized function implementations. - Shuo Li 002; Nasim Farahini; Ahmed Hemani; Kathrin Rosvall; Ingo Sander (CODES+ISSS, 2013)

Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework. - Shuo Li 002; Ahmed Hemani (DSD, 2013)

Global Control and Storage Synthesis for a System Level Synthesis Approach. - Shuo Li 002; Nasim Farahini; Ahmed Hemani (FCCM, 2013)

A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. - Shuo Li 002; Jamshaid Sarwar Malik; Shaoteng Liu; Ahmed Hemani (MES, 2013)

39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation. - Nasim Farahini; Shuo Li 002; Muhammad Adeel Tajammul; Muhammad Ali Shami; Guo Chen; Ahmed Hemani; Wei Ye (ISCAS, 2013)

Memory allocation and optimization in system-level architectural synthesis. - Shuo Li 002; Ahmed Hemani (ReCoSoC, 2013)

Case Study: Constraint Programming in a System Level Synthesis Framework. - Shuo Li 002; Ahmed Hemani (CP, 2014)

Three-Dimensional Design Space Exploration for System Level Synthesis. - Shuo Li 002; Ahmed Hemani (DSD, 2014)

Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver. - Shuo Li 002; Ahmed Hemani (FCCM, 2014)

Physical design aware system level synthesis of hardware. - Nasim Farahini; Ahmed Hemani; Hasan Sohofi; Shuo Li 002 (SAMOS, 2015)

System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems. - Shuo Li 002 (2015)