Shuo Wang

Affiliations:
  • Peking University, School of EECS, Beijing, China
  • University of Southern California, Los Angeles, CA, USA (former)


According to our database1, Shuo Wang authored at least 16 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs.
IEEE Trans. Computers, 2018

Efficient Recurrent Neural Networks using Structured Matrices in FPGAs.
Proceedings of the 6th International Conference on Learning Representations, 2018

C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications.
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018

2017
A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs.
Proceedings of the 54th Annual Design Automation Conference, 2017

A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs.
J. Comput. Sci. Technol., 2016

Performance-centric register file design for GPUs using racetrack memory.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Quantitative performance and power analysis of LTE using high level synthesis.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Hierarchical Deployment and Control of Energy Storage Devices in Data Centers.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015


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