A Parallel-Layered Belief-Propagation Decoder for Non-layered LDPC Codes. - Kun Guo 001; Yong Hei; Shushan Qiao (J. Commun., 2010)

A novel channel estimation algorithm in OFDM power line communication system. - Huidong Zhao; Yong Hei; Shushan Qiao (ASICON, 2011)

An improved phase digitization mechanism for fast-locking low-power all-digital PLLs. - Lin-Lin Xie; Yang Wang; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2017)

A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability. - Debin Kong; Jia Yuan; Shan-Shan Li; Heng You; Shushan Qiao (IEICE Electron. Express, 2018)

A low power and glitch-free circular rotation phase modulator for outphasing transmitter. - Yang Wang; Lin-Lin Xie; Yong Hei; Shushan Qiao (IEICE Electron. Express, 2018)

An anti-alias harmonic-reject phase modulation for digital outphasing transmitter. - Yang Wang; Lin-Lin Xie; Yong-sen Wang; Yong Hei; Shushan Qiao (IEICE Electron. Express, 2018)

A practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits. - Yi Yu; Jia Yuan; Lin-Lin Xie; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2018)

Design of low-power low-area asynchronous iterative multiplier. - Heng You; Yong Hei; Jia Yuan; Weidi Tang; Xu Bai; Shushan Qiao (IEICE Electron. Express, 2019)

An ultra-low leakage energy efficient level shifter with wide conversion range. - Heng You; Jia Yuan; Weidi Tang; Yi Yu; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2019)

A design method of CPR for wide voltage design. - Yi Yu; Zhi-jiu Zhu; Heng You; Jia Yuan; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2019)

Snake: An asynchronous pipeline for ultra-low-power applications. - Zhi-jiu Zhu; Yi Yu; Xu Bai; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2019)

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance. - Zhi-jiu Zhu; Yi Yu; Xu Bai; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2019)

A 8bits, 6.2ps resolution two-step time-to-digital converter with set-reset-based arbiters and signal tracking mechanism. - Yong-sen Wang; Song Cheng; A.-long Zhao; Heng You; Shushan Qiao (IEICE Electron. Express, 2020)

A fast and low-power level shifter for multi-supply voltage designs. - Jialu Yin; Jia Yuan; Heng You; Peng Wang 204; Shushan Qiao (IEICE Electron. Express, 2020)

Erratum: Snake: An asynchronous pipeline for ultra-low-power applications [IEICE Electronics Express Vol. 16 (2019) No. 12 pp. 20190293]. - Zhi-jiu Zhu; Yi Yu; Xu Bai; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2020)

Erratum: A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance [IEICE Electronics Express Vol. 16 (2019) No. 14 pp. 20190342]. - Zhi-jiu Zhu; Yi Yu; Xu Bai; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2020)

An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs. - Heng You; Jia Yuan; Weidi Tang; Shushan Qiao; Yong Hei (IEEE Trans. Circuits Syst., 2020)

A 0.5V 36nW 10-Transistor Power-on-Reset Circuit with High Accuracy. - Heng You; Jia Yuan; Zenghui Yu; Shushan Qiao (ISCAS, 2021)

An Efficient im2row-Based Fast Convolution Algorithm for ARM Cortex-M MCUs. - Peng Wang 204; Xiaoqin Wang; Rui Luo; Dingyi Wang; Mengjie Luo; Shushan Qiao; Yumei Zhou (IEEE Access, 2021)

A 8.83nW, 0.14ppm/℃ crystal oscillator using duty-cycling automatic amplitude control. - Yulian Wang; Xiaoyu Hu; Xinxin Ren; Heng You; Dashan Shi; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2021)

Area-energy efficient CORDICs using new elementary-angle-set and base-2 exponent expansions scheme. - Yong-sen Wang; Yu-qun Xue; Heng You; Shushan Qiao (IEICE Electron. Express, 2021)

Gradient Corrected Approximation for Binary Neural Networks. - Song Cheng; Zixuan Li; Yong-sen Wang; Wanbing Zou; Yumei Zhou; Delong Shang; Shushan Qiao (IEICE Trans. Inf. Syst., 2021)

Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation. - Heng You; Jia Yuan; Zenghui Yu; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Multi-type SRAM Test Structure with an Improved March LR Algorithm. - Xinshun Ning; Hongyong Yang; Mengdi Zhang; Yanji Wang; Ye Zhao; Shushan Qiao (APCCAS, 2022)

Improving The ResNet-based Respiratory Sound Classification Systems With Focal Loss. - Jun Li; Xiao Wang 022; Xiaoqin Wang; Shushan Qiao; Yumei Zhou (BioCAS, 2022)

Low-complex and Highly-performed Binary Residual Neural Network for Small-footprint Keyword Spotting. - Xiao Wang 022; Song Cheng; Jun Li; Shushan Qiao; Yumei Zhou; Yi Zhan (INTERSPEECH, 2022)

Accurate spectral testing algorithm of ADC with amplitude drift. - Jiangduo Fu; Zhong Yang; Jiayin Song; Shushan Qiao (IEICE Electron. Express, 2022)

A fully integrated RC oscillator with adaptive-body-biasing. - Zhi Li 090; Huidong Zhao; Jialu Yin; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2022)

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM. - Dashan Shi; Jia Yuan; Jialu Yin; Yulian Wang; Shushan Qiao (IEICE Electron. Express, 2022)

A 0.6V 1.76nW power on reset circuit with high accuracy. - Yulian Wang; Xiaoyu Hu; Xinxin Ren; Dashan Shi; Heng You; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2022)

A fully integrated GaAs HBT power amplifier with enhanced efficiency for 5-GHz WLAN applications. - Haohan Yang; Heng You; Shushan Qiao (IEICE Electron. Express, 2022)

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture. - Jialu Yin; Jia Yuan; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2022)

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. - Mengdi Zhang; Ye Zhao; Yong Chen 005; Paolo Crovetti; Yanji Wang; Xinshun Ning; Shushan Qiao (Sensors, 2022)

Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 2022, 22, 5852. - Mengdi Zhang; Ye Zhao; Yong Chen 005; Paolo Crovetti; Yanji Wang; Xinshun Ning; Shushan Qiao (Sensors, 2022)

Error-Diffusion Based Speech Feature Quantization for Small-Footprint Keyword Spotting. - Mengjie Luo; Dingyi Wang; Xiaoqin Wang; Shushan Qiao; Yumei Zhou (IEEE Signal Process. Lett., 2022)

An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology. - Heng You; Jia Yuan; Zenghui Yu; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM. - Dashan Shi; Heng You; Jia Yuan; Yulian Wang; Shushan Qiao (IEICE Trans. Electron., 2022)

Multi-grained Backend Fusion for Manipulation Region Location of Partially Fake Audio. - Jun Li; Lin Li; Mengjie Luo; Xiaoqin Wang; Shushan Qiao; Yumei Zhou (DADA@IJCAI, 2023)

A Binary Keyword Spotting System with Error-Diffusion Based Feature Binarization. - Dingyi Wang; Mengjie Luo; Lin Li; Xiaoqin Wang; Shushan Qiao; Yumei Zhou (INTERSPEECH, 2023)

An Ultra-Small Area and High-Sensitivity Wireless Receiver for ISM and MICS Band Application. - Wenya Chen; Haohan Yang; Shushan Qiao (IEEE Access, 2023)

AMA-Det: Enhancing Shared Head of One-Stage Object Detection With Adaptation, Merging, and Alignment. - Song Cheng; Feng-Yue Li; Shushan Qiao; Delong Shang; Yu-Mei Zhou (IEEE Access, 2023)

Blended Glial Cell's Spiking Neural Network. - Liying Tao; Pan Li; Meihua Meng; Zonglin Yang; Xiaozhuang Liu; Jinhua Hu; Ji Dong; Shushan Qiao; Tian-Chun Ye 001; Delong Shang (IEEE Access, 2023)

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR. - Wenya Chen; Qingsong Cai; Zhong Yang; Shushan Qiao (IEICE Electron. Express, 2023)

A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits. - Kangning Wang 004; Huidong Zhao; Jiliang Liu; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM. - Pengyuan Zhao; Huidong Zhao; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application. - Ang Yuan; Huidong Zhao; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism. - Zhou Wang 005; Haochen Du; Baoyi Han; Yanqing Xu; Xiaonan Tang; Yang Zhou; Zhe Zheng; Wenpeng Cui; Yanwei Xiong; Shaojun Wei; Shushan Qiao; Shouyi Yin (AICAS, 2024)

RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism. - Zhou Wang 005; Haochen Du; Baoyi Han; Yanqing Xu; Xiaonan Tang; Yang Zhou; Zhe Zheng; Wenpeng Cui; Yanwei Xiong; Shaojun Wei; Shushan Qiao; Shouyi Yin (AICAS, 2024)

SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing. - Zhou Wang 005; Haochen Du; Jiuren Zhou; Yanqing Xu; Xiaonan Tang; Tianchun Ye 001; Shaojun Wei; Shushan Qiao; Shouyi Yin (APCCAS, 2024)

GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications. - Zhou Wang 005; Haochen Du; Jiuren Zhou; Yang Zhou; Xiaonan Tang; Tianchun Ye 001; Shaojun Wei; Shushan Qiao; Shouyi Yin (APCCAS, 2024)

A 0.5V 18.6nW Bandgap Voltage Reference with A Low-Leakage Sample / Hold Circuit. - Gaigai Zhao; Zhi Li 090; Linnan Li; Zhenhao Huang; Huidong Zhao; Shushan Qiao (ICTA, 2024)

A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications. - Heng You; Dashan Shi; Delong Shang; Yumei Zhou; Shushan Qiao (ISCAS, 2024)

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks. - Zupei Gu; Shukao Dou; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEEE Access, 2024)

An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS. - Jiliang Liu; Huidong Zhao; Zhi Li 090; Kangning Wang 004; Shushan Qiao (IEEE Access, 2024)

Energy-efficient approximate multiplier with incomplete-sorted 4-2 compressor for neural network applications. - Lin Li; Yiying Jiang; Xiaoqin Wang; Shushan Qiao (IEICE Electron. Express, 2024)

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques. - Ji-liang Liu; Kangning Wang 004; Jia-lu Yin; Xue-long Zhao; Zhi Li 090; Hui-dong Zhao; Shushan Qiao (IEICE Electron. Express, 2024)

Differentiable architecture search with multi-dimensional attention for spiking neural networks. - Yilei Man; Linhai Xie; Shushan Qiao; Yumei Zhou; Delong Shang (Neurocomputing, 2024)

CS-TTD: Triplet Transformer for Compressive Hyperspectral Target Detection. - Qingyao Yang; Xiaoqin Wang; Long Chen; Yumei Zhou; Shushan Qiao (IEEE Trans. Geosci. Remote. Sens., 2024)

Compressive Hyperspectral Target Detection With Restricted Distribution Property. - Qingyao Yang; Xiaoqin Wang; Dingyi Wang; Baoying Yu; Yumei Zhou; Shushan Qiao (IEEE Trans. Geosci. Remote. Sens., 2024)

A Low-Power and Low-Latency Speech Feature Extractor Based on Time-Domain Filter Bank. - Baoying Yu; Mengjie Luo; Dingyi Wang; Xiaoqin Wang; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs. - Ang Yuan; Huidong Zhao; Xiao Wang 022; Zhi Li 090; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks. - Heng You; Weijun Li; Delong Shang; Yumei Zhou; Shushan Qiao (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme. - Zhou Wang 005; Haochen Du; Vivek Mohan; Jiuren Zhou; Zhou Shu; Yanqing Xu; Baoyi Han; Xiaonan Tang; Shushan Qiao; Shouyi Yin; Anil A. Bharath; Emmanuel M. Drakakis (ISCAS, 2025)

A 230-nA Quiescent Current and Enhanced Transient Performance DC-DC Converter with Suppressed Under/Overshoot for IoT SoCs. - Zhi Li 090; Huidong Zhao; Zhenhao Huang; Linnan Li; Shushan Qiao (ISCAS, 2025)

AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points. - Zitao Liang; Jiliang Liu; Kangning Wang 004; Linnan Li; Zhi Li 090; Huidong Zhao; Shushan Qiao (ISCAS, 2025)

GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism. - Zhou Wang 005; Haochen Du; Jiuren Zhou; Zhou Shu; Yanqing Xu; Vivek Mohan; Baoyi Han; Xiaonan Tang; Shushan Qiao; Shouyi Yin; Anil A. Bharath; Emmanuel M. Drakakis (ISCAS, 2025)

Hardware Friendly Transformer Optimization with Dynamic Attention Matrix Fusion. - Qingyao Yang; Xiaoqin Wang; Yumei Zhou; Qiang Li; Shushan Qiao (ISCAS, 2025)

An Ultra-Low-Power Fully-Static Contention-Free Single-Phase-Clock Flip-Flop With Low Area. - Yinglei Dong; Jia Yuan; Shushan Qiao; Ye Zhao (IEEE Access, 2025)

An Area-Efficient Continuous-Time Ising Machine Featuring Dynamic Threshold Annealing. - Yufeng Wu; Xiaofeng Li; Jiayin Song; Yi Zhan; Shushan Qiao (IEEE Access, 2025)

Subset-Selection Weight Post-Training Quantization Method for Learned Image Compression Task. - Jinru Yang; Xiaoqin Wang; Qiang Li; Shushan Qiao; Yumei Zhou (IEEE Access, 2025)

Hardware Implementation of Block Floating-Point FFT Based on Approximate Computation and Conflict-Free Access. - Xiaohui Zhang; Zenghui Yu; Shushan Qiao; Yi Zhan (IEEE Access, 2025)

An energy-efficient readout method based on weight-flip-store coding and quantization cycle skipping technology for computing in memory. - Shukao Dou; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2025)

Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145]. - Kangning Wang 004; Huidong Zhao; Jiliang Liu; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2025)

A 230 nW digital-based low noise bio-signal amplifier with symmetric differential-mode detection logic and cascaded Muller-C input stage. - Yadong Wang; Yi Zhan; Shushan Qiao; Xiaoyu Hu (IEICE Electron. Express, 2025)

A low-power and fast-response FSK transmitter. - Zhong Yang; Qingsong Cai; Jiangduo Fu; Shushan Qiao (IEICE Electron. Express, 2025)

An ultra-low-power CMOS image sensor with a new pixel structure in PWM mode featuring a programmable ramp generator for calibration. - Ziyuan Wang; Ye Zhao; Aoming Zhan; Jinyu Gao; Long Chen; Cunbiao Hao; Hongying Zhang; Shushan Qiao (Microelectron. J., 2025)

A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. - Jiliang Liu; Huidong Zhao; Zhi Li 090; Kangning Wang 004; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection. - Kangning Wang 004; Huidong Zhao; Zhi Li 090; Jiliang Liu; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation. - Shukao Dou; Zupei Gu; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2025)

DIME-Net: A Dual-Illumination Adaptive Enhancement Network Based on Retinex and Mixture-of-Experts. - Ziang Wang; Xiaoqin Wang; Dingyi Wang; Qiang Li; Shushan Qiao (CoRR, 2025)

Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs. - Minglong Jia; Pengyuan Zhao; Linnan Li; Xiang Li; Zhi Li 090; Huidong Zhao; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Accelerating Unstructured Sparse DNNs via Multilevel Partial Sum Reduction and PE Array-Level Load Balancing. - Chendong Xia; Qiang Li; Zhi Li 090; Bing Li 017; Huidong Zhao; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead. - Baoying Yu; Xiaoqin Wang; Dingyi Wang; Qiang Li; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)