Fault-tolerant designs for 256 Mb DRAM. - Toshiaki Kirihata; Yohji Watanabe; Hing Wong; John K. DeBrosse; Munehiro Yoshida; Daisuke Kato; Shuso Fujii; Matthew R. Wordeman; Peter Poechmueller; Stephen A. Parke; Yoshiaki Asao (IEEE J. Solid State Circuits, 1996)

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

Flexible test mode approach for 256-Mb DRAM. - Toshiaki Kirihata; Hing Wong; John K. DeBrosse; Yohji Watanabe; Takahiko Hara; Munehiro Yoshida; Matthew R. Wordeman; Shuso Fujii; Yoshiaki Asao; Bo Krsnik (IEEE J. Solid State Circuits, 1997)

Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. - Osamu Wada; Toshimasa Namekawa; Hiroshi Ito; Atsushi Nakayama; Shuso Fujii (ITC, 2004)

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. - Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; et al. (ISSCC, 2006)

Design of a 128-mb SOI DRAM using the floating body cell (FBC). - Takashi Ohsawa; Katsuyuki Fujita; Kosuke Hatsuda; Tomoki Higashi; Tomoaki Shino; Yoshihiro Minami; Hiroomi Nakajima; Mutsuo Morikado; Kazumi Inoh; Takeshi Hamamoto; Shigeyoshi Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2006)

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (ISSCC, 2009)

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (ISSCC, 2010)

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (IEEE J. Solid State Circuits, 2010)

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. - Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance. - Daisaburo Takashima; Yasushi Nagadomi; Kosuke Hatsuda; Yohji Watanabe; Shuso Fujii (IEEE J. Solid State Circuits, 2011)

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2011)

An Embedded DRAM Technology for High-Performance NAND Flash Memories. - Daisaburo Takashima; Mitsuhiro Noguchi; Noboru Shibata; Kazushige Kanda; Hiroshi Sukegawa; Shuso Fujii (IEEE J. Solid State Circuits, 2012)