A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. - Shunsuke Okumura; Yusuke Iguchi; Shusuke Yoshimoto; Hidehiro Fujiwara; Hiroki Noguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2009)

7T SRAM enabling low-energy simultaneous block copy. - Shunsuke Okumura; Shusuke Yoshimoto; Kosuke Yamaguchi; Yohei Nakata; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2010)

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. - Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2011)

A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19. - Shunsuke Okumura; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ESSCIRC, 2011)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. - Shusuke Yoshimoto; Takuro Amashita; D. Kozuwa; Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2011)

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. - Shunsuke Okumura; Yuki Kagiyama; Yohei Nakata; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Neutron-induced soft error rate estimation for SRAM using PHITS. - Shusuke Yoshimoto; Takuro Amashita; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2012)

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. - Shusuke Yoshimoto; Masaharu Terada; Youhei Umeki; Shunsuke Okumura; Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2012)

Bit error rate estimation in SRAM considering temperature fluctuation. - Yuki Kagiyama; Shunsuke Okumura; Koji Yanagida; Shusuke Yoshimoto; Yohei Nakata; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. - Masaharu Terada; Shusuke Yoshimoto; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. - Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. - Shunsuke Okumura; Hidehiro Fujiwara; Kosuke Yamaguchi; Shusuke Yoshimoto; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Electron., 2012)

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. - Shunsuke Okumura; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. - Shusuke Yoshimoto; Takuro Amashita; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. - Shusuke Yoshimoto; Takuro Amashita; Shunsuke Okumura; Koji Nii; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. - Shunsuke Okumura; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2013)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2013)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. - Shusuke Yoshimoto; Shinji Miyano; Makoto Takamiya; Hirofumi Shinohara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2013)

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. - Shusuke Yoshimoto; Shunsuke Okumura; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Tomoki Nakagawa; Yuki Kitahara; Koji Yanagida; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; et al. (BioCAS, 2014)

A 6T-4C shadow memory using plate line and word line boosting. - Tomoki Nakagawa; Shintaro Izumi; Shusuke Yoshimoto; Koji Yanagida; Yuki Kitahara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2014)

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. - Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A negative-resistance sense amplifier for low-voltage operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (ASP-DAC, 2015)

A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2015)

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. - Tomoki Nakagawa; Shintaro Izumi; Koji Yanagida; Yuki Kitahara; Shusuke Yoshimoto; Yohei Umeki; Haruki Mori; Hiroto Kitahara; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; et al. (ISCAS, 2015)

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Shusuke Yoshimoto; Tomoki Nakagawa; Yozaburo Nakai; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Hiroshi Nakajima; et al. (IEEE Trans. Biomed. Circuits Syst., 2015)

Implantable wireless 64-channel system with flexible ECoG electrode and optogenetics probe. - Shusuke Yoshimoto; Teppei Araki; Takafumi Uemura; Toshikazu Nezu; Tsuyoshi Sekitani; Takafumi Suzuki; Fumiaki Yoshida; Masayuki Hirata (BioCAS, 2016)

Wireless EEG patch sensor on forehead using on-demand stretchable electrode sheet and electrode-tissue impedance scanner. - Shusuke Yoshimoto; Teppei Araki; Takafumi Uemura; Toshikazu Nezu; Masaya Kondo; Kenichi Sasai; Masayuki Iwase; Hideki Satake; Akio Yoshida; Mitsuru Kikuchi; Tsuyoshi Sekitani (EMBC, 2016)

An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2016)

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. - Haruki Mori; Yohei Umeki; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2016)

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

A patch-type wireless forehead pulse oximeter for SpO2 measurement. - Afreen Azhari; Shusuke Yoshimoto; Toshikazu Nezu; Hirokazu Iida; Hiroki Ota; Yuki Noda; Teppei Araki; Takafumi Uemura; Tsuyoshi Sekitani; Katsuyuki Morii (BioCAS, 2017)

Wearable pulse wave velocity sensor using flexible piezoelectric film array. - Takumi Katsuura; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Shusuke Yoshimoto; Tsuyoshi Sekitani (BioCAS, 2017)

Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. - Fumika Tanabe; Shusuke Yoshimoto; Yuki Noda; Teppei Araki; Takafumi Uemura; Yoshinori Takeuchi; Masaharu Imai; Tsuyoshi Sekitani (EMBC, 2017)

Flexible organic TFT bio-signal amplifier using reliable chip component assembly process with conductive adhesive. - Shusuke Yoshimoto; Takafumi Uemura; Mihoko Akiyama; Yoshihiro Ihara; Satoshi Otake; Tomoharu Fujii; Teppei Araki; Tsuyoshi Sekitani (EMBC, 2017)

Flexible electronics for bio-signal monitoring in implantable applications. - Shusuke Yoshimoto; Teppei Araki; Takafumi Uemura; Yuki Noda; Tsuyoshi Sekitani (IEICE Electron. Express, 2017)

Noise Evaluation System for Biosignal Sensors Using Pseudo-Skin and Helmholtz Coil. - Misaki Inaoka; Shintaro Izumi; Shusuke Yoshimoto; Toshikazu Nezu; Yuki Noda; Teppei Araki; Takafumi Uemura; Tsuyoshi Sekitani (ISMICT, 2019)

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Printable Transparent Microelectrodes toward Mechanically and Visually Imperceptible Electronics. - Ashuya Takemoto; Teppei Araki; Takafumi Uemura; Yuki Noda; Shusuke Yoshimoto; Shintaro Izumi; Shuichi Tsuruta; Tsuyoshi Sekitani (Adv. Intell. Syst., 2020)

HARU Sleep: A Deep Learning-Based Sleep Scoring System With Wearable Sheet-Type Frontal EEG Sensors. - Shoya Matsumori; Kosei Teramoto; Hiroya Iyori; Takanori Soda; Shusuke Yoshimoto; Haruo Mizutani (IEEE Access, 2022)

Estimation of the Stages of Labor Using a Multichannel Electrohysterogram Sensor and Conditional Variational Autoencoder. - Minon Kushihashi; Shintaro Izumi; Hirokazu Iida; Shusuke Yoshimoto; Tsuyoshi Takiuchi; Kazuya Mimura; Takeshi Kanagawa; Aiko Kakigano; Tsuyoshi Sekitani; Masayuki Endoh; Tadashi Kimura; Hiroshi Kawaguchi 001 (EMBC, 2024)