Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. - Shuu'ichirou Yamamoto; Yusuke Shuto; Satoshi Sugahara (CICC, 2009)

Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service. - Ryosho Nakane; Yusuke Shuto; Hiroaki Sukegawa; Zhenchao Wen; Shuu'ichirou Yamamoto; Seiji Mitani; Masaaki Tanaka; Koichiro Inomata; Satoshi Sugahara (ESSDERC, 2013)

Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology. - Yusuke Shuto; Shuu'ichirou Yamamoto; Satoshi Sugahara (APCCAS, 2014)

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. - Yusuke Shuto; Shuu'ichirou Yamamoto; Satoshi Sugahara (DATE, 2015)

Energy performance of nonvolatile power-gating SRAM using SOTB technology. - Yusuke Shuto; Shuu'ichirou Yamamoto; Satoshi Sugahara (ESSCIRC, 2016)

Design and implementation of nonvolatile power-gating SRAM using SOTB technology. - Yusuke Shuto; Shuu'ichirou Yamamoto; Satoshi Sugahara (ISLPED, 2016)

Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters. - Daiki Kitagata; Shuu'ichirou Yamamoto; Satoshi Sugahara (NGCAS, 2018)

Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions. - Daiki Kitagata; Shuu'ichirou Yamamoto; Satoshi Sugahara (IEICE Electron. Express, 2020)

Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches. - Hayato Yoshida; Yusaku Shiotsu; Daiki Kitagata; Shuu'ichirou Yamamoto; Satoshi Sugahara (IEEE Open J. Circuits Syst., 2021)