A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. - Fumihiko Tachibana; Hironori Sato; Takahiro Yamashita; Hiroyuki Hara; Takeshi Kitahara; Shuou Nomura; Fumiyuki Yamane; Yoshiro Tsuboi; Keiko Seki; Shuuji Matsumoto; Yoshinori Watanabe; Mototsugu Hamada (CICC, 2008)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)