An integrated fault estimation and accommodation design for a class of complex networks. - Shuyao Cheng; Hao Yang 001; Bin Jiang 001 (Neurocomputing, 2016)

Decentralized Fault Tolerant Control for a Class of Interconnected Nonlinear Systems. - Shuai Shao 003; Hao Yang 001; Bin Jiang 001; Shuyao Cheng (IEEE Trans. Cybern., 2018)

BSHIFT: A Low Cost Deep Neural Networks Accelerator. - Yong Yu; Tian Zhi; Xuda Zhou; Shaoli Liu; Yunji Chen; Shuyao Cheng (Int. J. Parallel Program., 2019)

Cambricon-P: A Bitflow Architecture for Arbitrary Precision Computing. - Yifan Hao 001; Yongwei Zhao; Chenxiao Liu; Zidong Du; Shuyao Cheng; Xiaqing Li; Xing Hu 001; Qi Guo 001; Zhiwei Xu 002; Tianshi Chen 002 (MICRO, 2022)

Pushing the Limits of Machine Design: Automated CPU Design with AI. - Shuyao Cheng; Pengwei Jin; Qi Guo 001; Zidong Du; Rui Zhang 040; Yunhao Tian; Xing Hu 001; Yongwei Zhao; Yifan Hao 001; Xiangtao Guan; Husheng Han; Zhengyue Zhao; et al. (CoRR, 2023)

Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation. - Shuyao Cheng; Chongxiao Li; Zidong Du; Rui Zhang 040; Xing Hu 001; Xiaqing Li; Guanglin Xu; Yuanbo Wen; Qi Guo 001 (DAC, 2024)

Automated CPU Design by Learning from Input-Output Examples. - Shuyao Cheng; Pengwei Jin; Qi Guo 001; Zidong Du; Rui Zhang 040; Xing Hu 001; Yongwei Zhao; Yifan Hao 001; Xiangtao Guan; Husheng Han; Zhengyue Zhao; Ximing Liu; et al. (IJCAI, 2024)

AGON: Automated Design Framework for Customizing Processors from ISA Documents. - Chongxiao Li; Di Huang; Pengwei Jin; Tianyun Ma; Husheng Han; Shuyao Cheng; Yifan Hao 001; Yongwei Zhao; Guanglin Xu; Zidong Du; Rui Zhang 040; Xiaqing Li; et al. (CoRR, 2024)

QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies. - Shuyao Cheng; Rui Zhang 040; Wenkai He; Pengwei Jin; Chongxiao Li; Zidong Du; Xing Hu 001; Yifan Hao 001; Guanglin Xu; Yuanbo Wen; Ling Li 001; Qi Guo 001; et al. (CoRR, 2025)

CodeV-R1: Reasoning-Enhanced Verilog Generation. - Yaoyu Zhu; Di Huang; Han-Qi Lyu; Xiaoyun Zhang; Chongxiao Li; Wenxuan Shi; Yutong Wu; Jianan Mu; Jinghua Wang; Yang Zhao 013; Pengwei Jin; Shuyao Cheng; et al. (CoRR, 2025)

QiMeng: Fully Automated Hardware and Software Design for Processor Chip. - Rui Zhang 040; Yuanbo Wen; Shuyao Cheng; Di Huang; Shaohui Peng; Jiaming Guo; Pengwei Jin; Jiacheng Zhao; Tianrui Ma; Yaoyu Zhu; Yifan Hao 001; Yongwei Zhao; et al. (CoRR, 2025)

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs. - Pengwei Jin; Di Huang; Chongxiao Li; Shuyao Cheng; Yang Zhao 013; Xinyao Zheng; Jiaguo Zhu; Shuyi Xing; Bohan Dou; Rui Zhang 040; Zidong Du; Qi Guo 001; et al. (CoRR, 2025)