Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. - Shweta Chary; Michael L. Bushnell (VLSI Design, 2006)

Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. - Shweta Chary; Michael L. Bushnell (VLSI Design, 2006)