Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology. - Meenakshi Mishra; Shyam Akashe; Shyam Babu (BIC-TA (2), 2012)

Analysis and Simulation of Full Adder Design Using MTCMOS Technique. - Richa Saraswat; Shyam Akashe; Shyam Babu (BIC-TA (2), 2012)