Congestion Balancing Global Router. - Shyamapada Mukherjee; Jibesh Patra; Suchismita Roy (VDAT, 2013)

Multi terminal net routing for island style FPGAs using nearly-2-SAT computation. - Shyamapada Mukherjee; Suchismita Roy (VDAT, 2015)

SAT based solutions for detailed routing of island style FPGA architectures. - Shyamapada Mukherjee; Suchismita Roy (Microelectron. J., 2015)

Nearly-2-SAT Solutions for Segmented-Channel Routing. - Shyamapada Mukherjee; Suchismita Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction. - Sudeshna Kundu; Suchismita Roy; Shyamapada Mukherjee (ISED, 2017)

Lookahead legalization based global placement for heterogeneous FPGAs. - Sharbani Purkayastha; Shyamapada Mukherjee (ISED, 2017)

Via-Aware Dogleg Routing Using Boolean Satisfiability. - Shyamapada Mukherjee; Suchismita Roy (J. Circuits Syst. Comput., 2017)

IPplacer: An Efficient 0-1 Integer Programming Based Placement for VLSI Circuits. - Prasun Datta; Shyamapada Mukherjee (ICCCNT, 2018)

An Alternate Algorithmic Approach to FPGA Placement. - Shyamapada Mukherjee; A. Nainwal; C. C. Das; Sharbani Purkayastha (ICCCNT, 2018)

Spoken Language Recognition Using CNN. - Shyamapada Mukherjee; Neeraj Shivam; Astha Gangwal; Lokesh Khaitan; Amlan Jyoti Das (ICIT, 2019)

Gait Recognition using Segmented Motion Flow Energy Image. - Shyamapada Mukherjee; Kunal Chaudhary; Priya Jain; Bishal Paul (ICCCNT, 2019)

Architecture-aware routability-driven placer for large-scale mixed-size designs. - Prasun Datta; Shyamapada Mukherjee (IET Circuits Devices Syst., 2019)

Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology. - Sudeshna Kundu; Suchismita Roy; Shyamapada Mukherjee (J. Circuits Syst. Comput., 2020)

A Reward-based Framework for Recovery and Utilization of Recyclable Wastes using Blockchain. - Yagnyasenee Sen Gupta; Shyamapada Mukherjee (OCIT, 2022)

Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT. - Sudeshna Kundu; Suchismita Roy; Shyamapada Mukherjee (J. Circuits Syst. Comput., 2022)

PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing. - Sharbani Purkayastha; Shyamapada Mukherjee (Circuits Syst. Signal Process., 2023)

An extract-then-abstract based method to generate disaster-news headlines using a DNN extractor followed by a transformer abstractor. - Sumanta Banerjee; Shyamapada Mukherjee; Sivaji Bandyopadhyay; Partha Pakray (Inf. Process. Manag., 2023)

Testing the Effect of Hardware Trojans: A Case Study. - Sneh Agrawal; Shyamapada Mukherjee (ISED, 2024)

Hybrid Classical-Quantum Neural Network for n-Dimensional Embedding. - Arnab Das; Shyamapada Mukherjee (ISED, 2024)

Energy and Delay Optimization for Task Offloading in IoT-Fog Environment with Homogeneous Logical Instances on Fog Devices. - Ritarani Sahu; Suchismita Chinara; Prabhanjan Mishra; Shyamapada Mukherjee (ISED, 2024)

A Novel Unified Approach to Deepfake Detection of Images. - Lord Sen; Shyamapada Mukherjee (ISED, 2024)

Quantum Circuit Optimization Techniques Using Iterative Pre-Conditioned Gradient Descent. - Suvankar Tudu; Shyamapada Mukherjee (ISED, 2024)