Mixed-mode simulation and analog multilevel simulation. - Resve A. Saleh; Shyh-Jye Jou; A. Richard Newton (Kluwer, 1994)

Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. - Shyh-Jye Jou; Mei-Fang Perng; Chauchin Su; C. K. Wang (ISCAS, 1994)

An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. - Chauchin Su; Kychin Hwang; Shyh-Jye Jou (ITC, 1994)

Impulse response fault model and fault extraction for functional level analog circuit diagnosis. - Chauchin Su; Shenshung Chiang; Shyh-Jye Jou (ICCAD, 1995)

A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. - Wen-Hsing Hsieh; Shyh-Jye Jou; Chauchin Su (ISCAS, 1995)

Circuits Design Optimization Using Symbolic Approach. - Shyh-Jye Jou; Kou-Fong Liu; Chauchin Su (ISCAS, 1995)

Syndrome Simulation And Syndrome Test For Unscanned Interconnects. - Chauchin Su; Shyh-Shen Hwang; Shyh-Jye Jou; Yuan-Tzu Ting (Asian Test Symposium, 1996)

Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. - Chauchin Su; Shyh-Jye Jou; Yuan-Tzu Ting (ED&TC, 1996)

Metrology for analog module testing using analog testability bus. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou; Yuan-Tzu Ting (ICCAD, 1996)

Structural approach for performance driven ECC circuit synthesis. - Chauchin Su; Kathy Y. Chen; Shyh-Jye Jou (ASP-DAC, 1997)

Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou (ITC, 1997)

A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. - Shyh-Jye Jou; Chang-Yu Chen; En-Chung Yang; Chau-Chin Su (IEEE J. Solid State Circuits, 1997)

Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]. - Shyh-Jye Jou; Wei-Chung Cheng; Yu-Tao Lin (CICC, 1998)

An all digital phase-locked loop with modified binary search of frequency acquisition. - Shyh-Jye Jou; Ya-Lan Tsao; I-Ying Yang (ICECS, 1998)

Decentralized BIST Methodology for System Level Interconnects. - Chauchin Su; Shyh-Jye Jou (J. Electron. Test., 1999)

Fixed-Width Multiplier for DSP Application. - Shyh-Jye Jou; Hui-Hsuan Wang (ICCD, 2000)

A serial link transceiver for USB2 high-speed mode. - Shyh-Jye Jou; Shu-Hua Kuo; Jui-Ta Chiu; Chu King; Chien-Hsiung Lee; Tim Liu (ISCAS (4), 2001)

Low-power multiplierless FIR filter synthesizer based on CSD code. - Maw-Ching Lin; Chien-Lung Chen; Ding-Yu Shin; Chin-Hung Lin; Shyh-Jye Jou (ISCAS (4), 2001)

Low switching noise and load-adaptive output buffer design techniques. - Shyh-Jye Jou; Shu-Hua Kuo; Jui-Ta Chiu; Tin-Hao Lin (IEEE J. Solid State Circuits, 2001)

Intrinsic response for analog module testing using an analog testability bus. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou (ACM Trans. Design Autom. Electr. Syst., 2001)

An embedded DSP core for wireless communication. - Shyh-Jye Jou; Hsiao Ping Lee; Yi-Ting Chen; Ming Hsuan Tan; Ya-Lan Tsao (ISCAS (4), 2002)

Sub-word and reduced-width Booth multipliers for DSP applications. - Meng-Hung Tsai; Yi-Ting Chen; Wen-Sheng Cheng; Jun-Xian Teng; Shyh-Jye Jou (ISCAS (3), 2002)

5Gbps serial link transmitter with pre-emphasis. - Chih-Hsien Lin; Chung-Hong Wang; Shyh-Jye Jou (ASP-DAC, 2003)

Low-power digital CDMA receiver. - Ja-Sheng Liu; I-Hsin Chen; Yi-Chen Tsai; Shyh-Jye Jou (ASP-DAC, 2003)

Parameterized and low power DSP core for embedded systems. - Ya-Lan Tsao; Ming Hsuan Tan; Jun-Xian Teng; Shyh-Jye Jou (ISCAS (5), 2003)

Low-Power Embedded DSP Core for Communication Systems. - Ya-Lan Tsao; Wei-Hao Chen; Ming Hsuan Tan; Maw-Ching Lin; Shyh-Jye Jou (EURASIP J. Adv. Signal Process., 2003)

A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. - Kai-Yuan Jheng; Shyh-Jye Jou; An-Yeu Wu (ISCAS (5), 2004)

4/2 PAM serial link transmitter with tunable pre-emphasis. - Chih-Hsien Lin; Chang-Hsiao Tsai; Chih-Ning Chen; Shyh-Jye Jou (ISCAS (1), 2004)

A 12.5 Gbps CMOS input sampler for serial link receiver front end. - Shyh-Jye Jou; Chih-Hsien Lin; Yen-I Wang (ISCAS (2), 2005)

Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link. - Chih-Hsien Lin; Chang-Hsiao Tsai; Chih-Ning Chen; Shyh-Jye Jou (IEICE Trans. Electron., 2005)

Memory reduction ICFO estimation architecture for DVB-T. - Ting-Zhen Wei; Shyh-Jye Jou; Muh-Tian Shiue (ISCAS, 2006)

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling. - Hsiao-Yun Chen; Chih-Hsien Lin; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Parallel scrambler for high-speed applications. - Chih-Hsien Lin; Chih-Ning Chen; You-Jiun Wang; Ju-Yuan Hsiao; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System. - Chi-Shiung Lin; Yu-Chun Lin; Shyh-Jye Jou; Mun-Tian Shiou (CICC, 2007)

Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications. - Hsiao-Yun Chen; Shyh-Jye Jou (ICASSP (3), 2007)

Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H. - Wei-Chang Liu; Ting-Chen Wei; Shyh-Jye Jou (ISCAS, 2007)

Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. - Jiun-Yi Lin; Li-Rong Wang; Chia-Lin Hu; Shyh-Jye Jou (SoCC, 2007)

Design and analysis of digital data recovery circuits using oversampling. - Shyh-Jye Jou; Chih-Hsien Lin; Yen-Hung Chen; Zheng-Hong Li (IET Circuits Devices Syst., 2007)

A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization. - Ting-Chen Wei; Wei-Chang Liu; Chi-Yao Tseng; Syu-Siang Long; Shyh-Jye Jou; Muh-Tian Shiue (CICC, 2008)

Symbol and carrier frequency offset synchronization for IEEE802.16e. - Jyun-Nan Lin; Hsiao-Yun Chen; Ting-Chen Wei; Shyh-Jye Jou (ISCAS, 2008)

A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. - Li-Rong Wang; Yi-Wei Chiu; Chia-Lin Hu; Ming-Hsien Tu; Shyh-Jye Jou; Chung-Len Lee (ISCAS, 2008)

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. - Chih-Hao Liu; Shau-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE J. Solid State Circuits, 2008)

Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07). - Nicky Lu; Shyh-Jye Jou (IEEE J. Solid State Circuits, 2008)

A jointed mode detection and symbol detection scheme for DVB-T. - Wei-Ting Chen; Wei-Chang Liu; Shyh-Jye Jou (IEEE Trans. Consumer Electron., 2008)

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. - Shao-Wei Yen; Ming-Chih Hu; Chin-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (CICC, 2009)

10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop. - Yu-Chun Lin; Muh-Tian Shiue; Shyh-Jye Jou (ISCAS, 2009)

Asymmetrical Write-assist for single-ended SRAM operation. - Jihi-Yu Lin; Ming-Hsien Tu; Ming-Chien Tsai; Shyh-Jye Jou; Ching-Te Chuang (SoCC, 2009)

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. - Chih-Hao Liu; Chien-Ching Lin; Shao-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Low complexity synchronization design of an OFDM receiver for DVB-T/H. - Ting-Chen Wei; Wei-Chang Liu; Chi-Yao Tseng; Shyh-Jye Jou (IEEE Trans. Consumer Electron., 2009)

Perceptual multiband spectral subtraction for noise reduction in hearing aids. - Cheng-Wen Wei; Cheng-Chun Tsai; Tian-Sheuan Chang; Shyh-Jye Jou (APCCAS, 2010)

A Robust Channel Estimator for High-Mobility STBC-OFDM Systems. - Hsiao-Yun Chen; Meng-Lin Ku; Shyh-Jye Jou; Chia-Chi Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. - Ming-Hsien Tu; Jihi-Yu Lin; Ming-Chien Tsai; Shyh-Jye Jou; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. - Chia-Wen Chang; Shyh-Jye Jou; Yuan-Hua Chu (ASICON, 2011)

Digitally-controlled cell-based oscillator with multi-phase differential outputs. - Ming-Chiuan Su; Shyh-Jye Jou (ASICON, 2011)

Low power InfomaxICA with compensation strategy for binaural hearing-aid. - Fan-Chiang Yi; Ching-Wen Huang; Tai-Shih Chi; Shyh-Jye Jou (ISCAS, 2011)

8T single-ended sub-threshold SRAM with cross-point data-aware write operation. - Yi-Wei Chiu; Jihi-Yu Lin; Ming-Hsien Tu; Shyh-Jye Jou; Ching-Te Chuang (ISLPED, 2011)

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design. - Li-Rong Wang; Ming-Hsien Tu; Shyh-Jye Jou; Chung-Len Lee (IEICE Trans. Electron., 2011)

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. - Shao-Cheng Wang; Geng-Cing Lin; Yi-Wei Lin; Ming-Chien Tsai; Yi-Wei Chiu; Shyh-Jye Jou; Ching-Te Chuang; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (APCCAS, 2012)

A low-power body-channel communication system for binaural hearing aids. - Jou-Ling Chen; Jhih-Cing Sun; Yi-Hung Shen; Tzu-Hsien Sang; Tian-Sheuan Chang; Shyh-Jye Jou (BioCAS, 2012)

A 80-uW 2-Mb/s transceiver for human body channel binaural communication. - Jhih-Cing Sun; Jou-Ling Chen; Yi-Hung Shen; Shiu-Chain You; Shyh-Jye Jou; Tzu-Hsien Sang (BioCAS, 2012)

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. - Geng-Cing Lin; Shao-Cheng Wang; Yi-Wei Lin; Ming-Chien Tsai; Ching-Te Chuang; Shyh-Jye Jou; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (ISCAS, 2012)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

Testing strategies for a 9T sub-threshold SRAM. - Hao-Yu Yang; Chen-Wei Lin; Hung-Hsin Chen; Mango Chia-Tso Chao; Ming-Hsien Tu; Shyh-Jye Jou; Ching-Te Chuang (ITC, 2012)

Welcome from the general chairs. - Michel Brillouët; Shyh-Jye Jou; C. Patrick Yue (VLSI-DAT, 2012)

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. - Yi-Wei Lin; Ming-Chien Tsai; Hao-I Yang; Geng-Cing Lin; Shao-Cheng Wang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih (VLSI-DAT, 2012)

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. - Ming-Chien Tsai; Yi-Wei Lin; Hao-I Yang; Ming-Hsien Tu; Wei-Chiang Shih; Nan-Chun Lien; Kuen-Di Lee; Shyh-Jye Jou; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2012)

High throughput concurrent lookahead adaptive decision feedback equaliser. - Yu-Chun Lin; Shyh-Jye Jou; Muh-Tian Shiue (IET Circuits Devices Syst., 2012)

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. - Ming-Hsien Tu; Jihi-Yu Lin; Ming-Chien Tsai; Chien-Yu Lu; Yuh-Jiun Lin; Meng-Hsueh Wang; Huan-Shun Huang; Kuen-Di Lee; Wei-Chiang Shih; Shyh-Jye Jou; Ching-Te Chuang (IEEE J. Solid State Circuits, 2012)

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. - Shao-Wei Yen; Shiang-Yu Hung; Chih-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. - Chien-Yu Lu; Ming-Hsien Tu; Hao-I Yang; Ya-Ping Wu; Huan-Shun Huang; Yuh-Jiun Lin; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Sub µW Noise Reduction for CIC Hearing Aids. - Cheng-Wen Wei; Sheng-Jie Su; Tian-Sheuan Chang; Shyh-Jye Jou (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. - Ming-Chiuan Su; Wei-Zen Chen; Pei-Si Wu; Yu-Hsian Chen; Chao-Cheng Lee; Shyh-Jye Jou (CICC, 2013)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c. - Wei-Chang Liu; Fu-Chun Yeh; Ting-Chen Wei; Ya-Shiue Huang; Tai-Yang Liu; Shen-Jui Huang; Ching-Da Chan; Shyh-Jye Jou; Sau-Gee Chen (ISCAS, 2013)

A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Shyh-Jye Jou; Ching-Te Chuang (ISLPED, 2013)

A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids. - Yi-Cheng Huang; Fan-Chiang Yi; Shyh-Jye Jou (SiPS, 2013)

Spatial-cue-based multi-band binaural noise reduction for hearing aids. - Cheng-Yen Yang; Wen-Sheng Chou; Kuo-Chiang Chang; Chih-Wei Liu; Tai-Shih Chi; Shyh-Jye Jou (SiPS, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)

Power and area reduction in multi-stage addition using operand segmentation. - Ching-Da Chan; Wei-Chang Liu; Chia-Hsiang Yang; Shyh-Jye Jou (VLSI-DAT, 2013)

A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design. - Li-Rong Wang; Kai-Yu Lo; Shyh-Jye Jou (IEICE Trans. Electron., 2013)

A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems. - Hsiao-Yun Chen; Wei-Kai Chang; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band. - Wei-Chang Liu; Fu-Chun Yeh; Ting-Chen Wei; Ching-Da Chan; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

STBC-OFDM Downlink Baseband Receiver for Mobile WMAN. - Hsiao-Yun Chen; Jyun-Nan Lin; Hsiang-Sheng Hu; Shyh-Jye Jou (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. - Cheng-Yen Yang; Chih-Wei Liu; Shyh-Jye Jou (ICASSP, 2014)

An ultra-low voltage hearing aid chip using variable-latency design technique. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Chih-Wei Liu; Yuan-Hua Chu; Shyh-Jye Jou (ISCAS, 2014)

An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band. - Wei-Chang Liu; Fu-Chun Yeh; Chia-Yi Wu; Ting-Chen Wei; Ya-Shiue Huang; Shen-Jui Huang; Ching-Da Chan; Shyh-Jye Jou; Sau-Gee Chen (ISCAS, 2014)

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. - Chao-Kuei Chung; Chien-Yu Lu; Zhi-Hao Chang; Shyh-Jye Jou; Ching-Te Chuang; Ming-Hsien Tu; Yu-Hsian Chen; Yong-Jyun Hu; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (SoCC, 2014)

A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. - Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou; Wen-Tai Wang; Reed Lee (SoCC, 2014)

Blind ICA detection based on second-order cone programming for MC-CDMA systems. - Chih-Wei Jen; Shyh-Jye Jou (EURASIP J. Adv. Signal Process., 2014)

Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application. - Cheng-Wen Wei; Cheng-Chun Tsai; FanJiang Yi; Tian-Sheuan Chang; Shyh-Jye Jou (IET Circuits Devices Syst., 2014)

Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing. - Yi FanChiang; Cheng-Wen Wei; Yi-Le Meng; Yu-Wen Lin; Shyh-Jye Jou; Tian-Sheuan Chang (IEEE ACM Trans. Audio Speech Lang. Process., 2014)

Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing". - Yi FanChiang; Cheng-Wen Wei; Yi-Le Meng; Yu-Wen Lin; Shyh-Jye Jou; Tian-Sheuan Chang (IEEE ACM Trans. Audio Speech Lang. Process., 2014)

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures. - Sau-Gee Chen; Shen-Jui Huang; Mario Garrido; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application. - Yu-Jui Chen; Cheng-Wen Wei; Yi FanChiang; Yi-Le Meng; Yi-Cheng Huang; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Yuan-Hua Chu; Shyh-Jye Jou; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. - Nan-Chun Lien; Li-Wei Chu; Chien-Hen Chen; Hao-I Yang; Ming-Hsien Tu; Paul-Sen Kan; Yong-Jyun Hu; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead. - Wen-Quan He; Yu-Chun Lin; Jui-Yi Hung; Shyh-Jye Jou (ASICON, 2015)

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. - Nicholas Preyss; Christian Senning; Andreas Burg 001; Wei-Chang Liu; Chun-Yi Liu 001; Shyh-Jye Jou (A-SSCC, 2015)

Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system. - Pranav Arya; Liang-Yu Huang; Wei-Chang Liu; Hsin-Ting Chang; Chih-Wei Jen; Chih-Feng Wu; Shyh-Jye Jou (ICCE-TW, 2015)

A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. - Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou; Wen-Tai Wang; Reed Lee (ISCAS, 2015)

A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems. - Henry Lopez Davila; Chun-Yi Liu 001; Wei-Chang Liu; Shen-Jui Huang; Shyh-Jye Jou; Sau-Gee Chen (SoCC, 2015)

A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems. - Liang-Yu Huang; Chia-Yi Wu; Chun-Yi Liu 001; Wei-Chang Liu; Chih-Feng Wu; Shyh-Jye Jou (VLSI-DAT, 2015)

A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications. - Chia-Wen Chang; Yuan-Hua Chu; Shyh-Jye Jou (IEICE Trans. Electron., 2015)

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation. - Wen-Quan He; Yuan-Ho Chen; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. - Wei-Chang Liu; Ting-Chen Wei; Ya-Shiue Huang; Ching-Da Chan; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. - Ming-Chiuan Su; Wei-Zen Chen; Pei-Si Wu; Yu-Hsian Chen; Chao-Cheng Lee; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. - Chien-Yu Lu; Ching-Te Chuang; Shyh-Jye Jou; Ming-Hsien Tu; Ya-Ping Wu; Chung-Ping Huang; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. - Ming-Chiuan Su; Shyh-Jye Jou; Wei-Zen Chen (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Interference measurement and analysis of full-duplex wireless system in 60 GHz band. - Hung-Wei Yang; Yongyu He; Chih-Wei Jen; Chun-Yi Liu 001; Shyh-Jye Jou; Xuefeng Yin; Meng Ma; Bingli Jiao (APCCAS, 2016)

Error-resilient sequential cells with successive time borrowing for stochastic computing. - Wei-Chang Liu; Ching-Da Chan; Shuo-An Huang; Chi-Wei Lo; Chia-Hsiang Yang; Shyh-Jye Jou (ICASSP, 2016)

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. - Yi-Wei Chiu; Yu-Hao Hu; Jun-Kai Zhao; Shyh-Jye Jou; Ching-Te Chuang (ISCAS, 2016)

A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver. - Chun-Yi Liu 001; Meng-Siou Sie; Edmund Wen Jen Leong; Yu-Cheng Yao; Chih-Wei Jen; Shyh-Jye Jou (ISCAS, 2016)

Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series. - Wen-Quan He; Yuan-Ho Chen; Shyh-Jye Jou (Circuits Syst. Signal Process., 2016)

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. - Chia-Wen Chang; Kai-Yu Lo; Hossameldin A. Ibrahim; Ming-Chiuan Su; Yuan-Hua Chu; Shyh-Jye Jou (IEICE Trans. Electron., 2016)

A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems. - Cheng-Yen Yang; Chih-Wei Liu; Shyh-Jye Jou (IEEE ACM Trans. Audio Speech Lang. Process., 2016)

An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver. - Chun-Yi Liu 001; Meng-Siou Sie; Edmund Wen Jen Leong; Yu-Cheng Yao; Henry Lopez Davila; Chih-Wei Jen; Wei-Chang Liu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver. - Chih-Feng Wu; Wei-Chang Liu; Chia-Chun Tsui; Chun-Yi Liu 001; Meng-Siou Sie; Shyh-Jye Jou (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver. - Hsun-Wei Chan; Chang-Ting Wu; Chih-Wei Jen; Chun-Yi Liu 001; Wei-Che Lee; Shyh-Jye Jou (ASICON, 2017)

Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band. - Chun-Yi Liu 001; Yu-Cheng Yao; Meng-Siou Sie; Edmund Wen Jen Leong; Henry Lopez Davila; Chih-Wei Jen; Shyh-Jye Jou (ISCAS, 2017)

A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band. - Chun-Yi Liu 001; Edmund Wen Jen Leong; Chang-Ting Wu; Meng-Siou Sie; Henry Lopez Davila; Chih-Wei Jen; Shyh-Jye Jou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel. - Chun-Yi Liu 001; Meng-Siou Sie; Edmund Wen Jen Leong; Yu-Cheng Yao; Chih-Wei Jen; Wei-Chang Liu; Chih-Feng Wu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band. - Chih-Wei Jen; Hung-Wei Yang; Hsun-Wei Chan; Hung-Chih Liu; Henry Lopez Davila; Chun-Yi Liu 001; Shyh-Jye Jou (ISCAS, 2018)

A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems. - Chee-Kit Ng; Yu-Chun Lin; Wei-Chang Liu; Chih-Feng Wu; Shyh-Jye Jou (ISCAS, 2018)

Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. - Yu-Cheng Su; Kang-Yu Chang; Yu-Tung Chin; Chia-Wen Chang; Shyh-Jye Jou (ASICON, 2019)

A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications. - Kang-Lun Chiu; Hsun-Wei Chan; Wei-Che Lee; Chang-Ting Wu; Henry Lopez Davila; Hung-Chih Liu; Meng-Yuan Huang; Chun-Yi Liu 001; Tsai-Hua Lee; Hsin-Ting Chang; Chih-Wei Jen; Nien-Hsiang Chang; et al. (A-SSCC, 2019)

Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line. - C. Y. He; K. H. Tang; T. S. Chen; K. Y. Chang; C. H. Lin; K. Sato; Shyh-Jye Jou; P. H. Chen; H. M. Chen; B. D. Rong; K. Itoh (A-SSCC, 2019)

A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems. - Chee-Kit Ng; Kang-Lun Chiu; Yu-Chun Lin; Shyh-Jye Jou (ISCAS, 2019)

A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems. - Chee-Kit Ng; Yu-Chun Lin; Shyh-Jye Jou (VLSI-DAT, 2019)

A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC. - Hung-Chih Liu; Hsun-Wei Chan; Henry Lopez Davila; Kang-Lun Chiu; Chih-Wei Jen; Ngoc-Giang Doan; Zheng-Chun Huang; Hsin-Ting Chang; Nien-Hsiang Chang; Pei-Yun Tsai 001; Yen-Cheng Kuan; Shyh-Jye Jou (A-SSCC, 2020)

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. - Hung-Ming Chen; Chia-Lin Hu; Kang-Yu Chang; Alexandra Küster; Yu-Hsien Lin; Po-Shen Kuo; Wei-Tung Chao; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ICCAD, 2020)

Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System. - Ngoc-Giang Doan; Hung-Chih Liu; Chih-Wei Jen; Shyh-Jye Jou (ISCAS, 2020)

Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access. - Kang-Lun Chiu; Pai-Hsiang Shen; Bing-Ru Lin; Wei-Han Hsiao; Shyh-Jye Jou; Chia-Chi Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm. - Henry Lopez Davila; Hsun-Wei Chan; Kang-Lun Chiu; Pei-Yun Tsai 001; Shyh-Jye Jou (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. - Chia-Chen Chang; Yu-Tung Chin; Hossameldin A. Ibrahim; Kang-Yu Chang; Shyh-Jye Jou (ISCAS, 2021)

On Reconfiguring Memory-Centric AI Edge Devices for CIM. - Hung-Ming Chen; Cheng-En Ni; Kang-Yu Chang; Tzu-Chieh Chiang; Shih-Han Chang; Cheng-Yu Chiang; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ISOCC, 2021)

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. - Yu-Hsien Lin; Chi Liu; Chia-Lin Hu; Kang-Yu Chang; Jia-Yin Chen; Shyh-Jye Jou (VLSI-DAT, 2021)

A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems. - Hsun-Wei Chan; Wei-Che Lee; Kang-Lun Chiu; Chih-Wei Jen; Shyh-Jye Jou (IEEE Trans. Very Large Scale Integr. Syst., 2021)

DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. - Bo-Cheng Lai; Tzu-Chieh Chiang; Po-Shen Kuo; Wan-Ching Wang; Yan-Lin Hung; Hung-Ming Chen; Chien-Nan Liu; Shyh-Jye Jou (DATE, 2022)

Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique. - Kang-Lun Chiu; Hsun-Wei Chan; Hsuan-Ping Chiu; Chun-Yi Liu 001; Chih-Wei Jen; Shyh-Jye Jou (ISCAS, 2022)

Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter. - Shen-Zhe Lu; Nai-Cheng Xue; Hung-Chih Liu; Chih-Wei Jen; Shyh-Jye Jou (ISCAS, 2022)

Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System. - Chung-Lun Tu; Tse-Yuan Lin; Kang-Lun Chiu; Shyh-Jye Jou; Pei-Yun Tsai 001 (ISCAS, 2022)

On Optimizing Capacitor Array Design for Advanced Node SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Kang-Yu Chang; Mark Po-Hung Lin; Shyh-Jye Jou; Hung-Yu Chen; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2022)

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. - Chi Liu; Shao-Tzu Li; Tong-Lin Pan; Cheng-En Ni; Yun Sung; Chia-Lin Hu; Kang-Yu Chang; Tuo-Hung Hou; Tian-Sheuan Chang; Shyh-Jye Jou (VLSI-DAT, 2022)

A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization. - Yu-Hsiang Chiang; Tian-Sheuan Chang; Shyh-Jye Jou (CoRR, 2022)

Hardware-Robust In-RRAM-Computing for Object Detection. - Yu-Hsiang Chiang; Cheng-En Ni; Yun Sung; Tuo-Hung Hou; Tian-Sheuan Chang; Shyh-Jye Jou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System. - Hung-Chih Liu; Zheng-Chun Huang; Ngoc-Giang Doan; Chih-Wei Jen; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization. - Yu-Hsiang Chiang; Tian-Sheuan Chang; Shyh-Jye Jou (IEEE Trans. Very Large Scale Integr. Syst., 2022)

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Mark Po-Hung Lin; Yu-Szu Chung; Shyh-Jye Jou; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2023)

Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter. - Chung-Lun Tu; Chin-Ming Chang; Shyh-Jye Jou (ISCAS, 2023)

Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications. - Henry Lopez Davila; Tsung-Han Wu; Shyh-Jye Jou; Sau-Gee Chen; Pei-Yun Tsai 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers. - Chih-Wei Jen; Hung-Chih Liu; Zheng-Chun Huang; Nai-Cheng Xue; Shyh-Jye Jou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. - Kuan-Chih Lin; Hao Zuo; Hsiang-Yu Wang; Yuan-Ping Huang; Ci-Hao Wu; Yan-Cheng Guo; Shyh-Jye Jou; Tuo-Hung Hou; Tian-Sheuan Chang (DATE, 2024)

Online Self-Adaptive Estimation and Compensation Design for DC Voltage Offset, Frequency-Independent, and Frequency-Dependent IQ Mismatch in Sub-THz Digital Baseband Transceiver. - Chia-Jung Lee; Chung-Lun Tu; Shyh-Jye Jou (ISCAS, 2024)

Channel Estimation and Equalization Design with SNR Decision Based Universal Threshold for Sub-THz Single Carrier Baseband Receiver. - Feng-Ju Liao; Chung-Lun Tu; Shyh-Jye Jou (ISCAS, 2024)

A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. - Tsung-Han Wu; Ching Liang Yeh; Yi-Shan Huang; Shyh-Jye Jou (ISCAS, 2024)

Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. - Bo-Han Li; Kuan-Chih Lin; Hao Zuo; Po-Cheng Pan; Hung-Ming Chen; Shyh-Jye Jou; Chien-Nan Jimmy Liu; Bo-Cheng Lai (MWSCAS, 2024)

A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion. - Wei-En Huang; Yi-Shan Huang; Shyh-Jye Jou (ISCAS, 2025)

Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model. - Chung-Lun Tu; Chen-Yuan Tseng; Wei-Che Lee; Kang-Lun Chiu; Pei-Yun Tsai 001; Shyh-Jye Jou (IEEE Open J. Circuits Syst., 2025)