Designing Self-Testable Cellular Arrays. - Cheng-Wen Wu; Shyue-Kung Lu (ICCD, 1991)

C-testable design techniques for iterative logic arrays. - Shyue-Kung Lu; Jen-Chuan Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Cell delay fault testing for iterative logic arrays. - Shyue-Kung Lu; Cheng-Wen Wu; Ruei-Zong Hwang (J. Electron. Test., 1996)

Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. - Shyue-Kung Lu; Sy-Yen Kuo; Cheng-Wen Wu (IEEE Trans. Computers, 1997)

Defect Level Prediction Using Multi-Model Fault Coverage. - Shyue-Kung Lu; Tsung-Ying Lee; Cheng-Wen Wu (Asian Test Symposium, 1999)

A novel approach to testing LUT-based FPGAs. - Shyue-Kung Lu; Cheng-Wen Wu (ISCAS (1), 1999)

A Testable/Fault Tolerant FFT Processor Design. - Shyue-Kung Lu; Jen-Sheng Shih; Cheng-Wen Wu (Asian Test Symposium, 2000)

Built-in self-test and fault diagnosis for lookup table FPGAs. - Shyue-Kung Lu; Jen-Sheng Shih; Cheng-Wen Wu (ISCAS, 2000)

Testing Configurable LUT-Based FPGAs. - Shyue-Kung Lu; Jen-Sheng Shih (J. Inf. Sci. Eng., 2000)

A Profit Evaluation System (PES) for logic cores at early design stage. - Shyue-Kung Lu; Tsung-Ying Lee; Cheng-Wen Wu (ICECS, 2001)

Built-In self-repair for divided word line memory. - Shyue-Kung Lu; Chih-Hsien Hsu (ISCAS (4), 2001)

Novel Fault-Tolerant Techniques for High Capacity RAMs. - Chih-Hsien Hsu; Shyue-Kung Lu; Sy-Yen Kuo (PRDC, 2001)

Fault-tolerance design of memory systems based on DBL structures. - Chih-Hsien Hsu; Shyue-Kung Lu (APCCAS (1), 2002)

Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's. - Shyue-Kung Lu; Chung-Yang Chen (Asian Test Symposium, 2002)

Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. - Shyue-Kung Lu; Chien-Hung Yeh (Asian Test Symposium, 2002)

Enhancing Delay Fault Testability for Iterative Logic Array. - Shyue-Kung Lu; Chien-Hung Yeh (PRDC, 2002)

OBDD-based evaluation of k-terminal network reliability. - Fu-Min Yeh; Shyue-Kung Lu; Sy-Yen Kuo (IEEE Trans. Reliab., 2002)

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs. - Shyue-Kung Lu; Fu-Min Yeh; Jen-Sheng Shih (VLSI Design, 2002)

Combinational circuit fault diagnosis using logic emulation. - Shyue-Kung Lu; Jian-Long Chen; Cheng-Wen Wu; Ken-Feng Chang; Shi-Yu Huang (ISCAS (5), 2003)

A Novel Built-In Self-Repair Approach for Embedded RAMs. - Shyue-Kung Lu (J. Electron. Test., 2003)

Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. - Hong-Chou Kao; Ming-Fu Tsai; Shi-Yu Huang; Cheng-Wen Wu; Wen-Feng Chang; Shyue-Kung Lu (J. Inf. Sci. Eng., 2003)

Testing and Diagnosis Techniques for LUT-Based FPGA's. - Shyue-Kung Lu; Hung-Chin Wu; Shoei-Jia Yan; Yu-Cheng Tsai (Asian Test Symposium, 2004)

Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model. - Shyue-Kung Lu; Mau-Jung Lu (DELTA, 2004)

Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. - Shyue-Kung Lu; Shih-Chang Huang (MTDT, 2004)

Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors. - Shyue-Kung Lu; Chien-Hung Yeh; Han-Wen Lin (PRDC, 2004)

Defect Level Prediction Using Multi-Model Fault Coverage. - Shyue-Kung Lu (IEICE Trans. Inf. Syst., 2004)

A BIRA algorithm for embedded memories with 2D redundancy. - Shyue-Kung Lu; Yu-Cheng Tsai; Shih-Chang Huang (MTDT, 2005)

A Multi-Faceted Approach towards Spam-Resistible Mail. - Ming-Wei Wu; Yennun Huang; Shyue-Kung Lu; Ing-Yi Chen; Sy-Yen Kuo (PRDC, 2005)

Design-for-testability and fault-tolerant techniques for FFT processors. - Shyue-Kung Lu; Jen-Sheng Shih; Shih-Chang Huang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy. - Shyue-Kung Lu; Chun-Lin Yang; Han-Wen Lin (ACIS-ICIS, 2006)

Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits. - Shyue-Kung Lu; Ting-Yu Chen; Wei-Yuan Liu (PRDC, 2006)

A Scalable Port Forwarding for P2P-Based Wi-Fi Applications. - Ming-Wei Wu; Yennun Huang; Ing-Yi Chen; Shyue-Kung Lu; Sy-Yen Kuo (WASA, 2006)

Fault tolerance techniques for high capacity RAM. - Shyue-Kung Lu; Chih-Hsien Hsu (IEEE Trans. Reliab., 2006)

Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. - Shyue-Kung Lu; Yu-Chen Tsai; Chih-Hsien Hsu; Kuo-Hua Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. - Chun-Lin Yang; Yuang-Cheng Hsiao; Shyue-Kung Lu (PRDC, 2007)

Low-Power Built-In Self-Test Techniques for Embedded SRAMs. - Shyue-Kung Lu; Yuang-Cheng Hsiao; Chia-Hsiu Liu; Chun-Lin Yang (VLSI Design, 2007)

Built-In Self-Repair Techniques for Heterogeneous Memory Cores. - Zhen-Yu Wang; Yi-Ming Tsai; Shyue-Kung Lu (PRDC, 2009)

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. - Shyue-Kung Lu; Chun-Lin Yang; Yuang-Cheng Hsiao; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. - Shyue-Kung Lu; Yin Chen; Shi-Yu Huang; Cheng Wu (IEEE Des. Test Comput., 2011)

On test and repair of 3D random access memory. - Cheng-Wen Wu; Shyue-Kung Lu; Jin-Fu Li 001 (ASP-DAC, 2012)

Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. - Shyue-Kung Lu; Tsu-Lin Li; Pony Ning (Asian Test Symposium, 2012)

Improving Reusability of Test Symbols for Test Data Compression. - Shyue-Kung Lu; Ya-Chen Huang (J. Inf. Sci. Eng., 2012)

Yield enhancement techniques for 3-dimensional random access memories. - Shyue-Kung Lu; Tin-Wei Chang; Han-Yu Hsu (Microelectron. Reliab., 2012)

Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs. - Shyue-Kung Lu; Zhen-Yu Wang; Yi-Ming Tsai; Jiann-Liang Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. - Masaki Hashizume; Tomoaki Konishi; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (Asian Test Symposium, 2013)

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. - Shyue-Kung Lu; Hao-Cheng Jheng; Masaki Hashizume; Jiun-Lang Huang; Pony Ning (Asian Test Symposium, 2013)

Error-tolerance evaluation and design techniques for motion estimation computing arrays. - Shyue-Kung Lu; Ming-Chang Chen; Yen-Chi Chen (IOLTS, 2013)

Efficient test and repair architectures for 3D TSV-based random access memories. - Shyue-Kung Lu; Uang-Chang Lu; Seng-Wen Pong; Hao-Cheng Cheng (VLSI-DAT, 2013)

An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs. - Tsu-Lin Li; Masaki Hashizume; Shyue-Kung Lu (IEICE Trans. Inf. Syst., 2013)

Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. - Shyue-Kung Lu; Huan-Hua Huang; Jiun-Lang Huang; Pony Ning (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A built-in supply current test circuit for electrical interconnect tests of 3D ICs. - Masaki Hashizume; Shoichi Umezu; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2014)

Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. - Shyue-Kung Lu; Hao-Cheng Jheng; Hao-Wei Lin; Masaki Hashizume; Seiji Kajihara (ATS, 2014)

Efficient test length reduction techniques for interposer-based 2.5D ICs. - Shyue-Kung Lu; Huai-Min Li; Masaki Hashizume; Jin-Hua Hong; Zheng-Ru Tsai (VLSI-DAT, 2014)

A Power Saving Mechanism for Multimedia Streaming Services in Cloud Computing. - Yi-Wei Ma; Jiann-Liang Chen; Ching-Hesign Chou; Shyue-Kung Lu (IEEE Syst. J., 2014)

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. - Kosuke Nanbara; Akihiro Odoriba; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2015)

Electrical interconnect test method of 3D ICs by injected charge volume. - Daisuke Suga; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2015)

An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories. - Shyue-Kung Lu; Hao-Wei Lin; Masaki Hashizume (ASICON, 2015)

Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories. - Shyue-Kung Lu; Cheng-Ju Tsai; Masaki Hashizume (ATS, 2015)

Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs. - Shyue-Kung Lu; Shu-Ling Lin; Hao-Wei Lin; Masaki Hashizume (VLSI-DAT, 2015)

Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. - Shyue-Kung Lu; Tsu-Lin Li; Masaki Hashizume; Jiann-Liang Chen (IEEE Trans. Computers, 2015)

Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories. - Shyue-Kung Lu; Shang-Xiu Zhong; Masaki Hashizume (ATS, 2016)

Online slack-time binning for IO-registered die-to-die interconnects. - Chih-Chieh Zheng; Shi-Yu Huang; Shyue-Kung Lu; Ting-Chi Wang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2016)

Integrated Heterogeneous Infrastructure for Indoor Positioning. - Yi-Wei Ma; Jiann-Liang Chen; Yao-Hong Tsai; Pen-Chan Chou; Shyue-Kung Lu; Sy-Yen Kuo (SpaCCS Workshops, 2016)

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. - Widianto; Masaki Hashizume; Shohei Suenaga; Hiroyuki Yotsuyanagi; Akira Ono; Shyue-Kung Lu; Zvi Roth (IEICE Trans. Inf. Syst., 2016)

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories. - Shyue-Kung Lu; Cheng-Ju Tsai; Masaki Hashizume (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. - Ayumu Kambara; Hiroyuki Yotsuyanagi; Daichi Miyoshi; Masaki Hashizume; Shyue-Kung Lu (ATS, 2017)

Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. - Shyue-Kung Lu; Shu-Chi Yu; Masaki Hashizume; Hiroyuki Yotsuyanagi (ATS, 2017)

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. - Michiya Kanda; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (DFT, 2017)

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume. - Kouhei Ohtani; Naho Osato; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (ISCIT, 2017)

Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power. - Shyue-Kung Lu; Hung-Kai Huang (ITC-Asia, 2017)

Progressive ECC Techniques for Phase Change Memory. - Shyue-Kung Lu; Hui-Ping Li; Kohei Miyase (ATS, 2018)

Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory. - Shyue-Kung Lu; Hui-Ping Li; Kohei Miyase (IOLTS, 2018)

Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories. - Shyue-Kung Lu; Hao-Cheng Jheng; Hao-Wei Lin; Masaki Hashizume (J. Electron. Test., 2018)

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories. - Shyue-Kung Lu; Shang-Xiu Zhong; Masaki Hashizume (J. Electron. Test., 2018)

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs. - Fara Ashikin; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu; Zvi Roth (IEICE Trans. Inf. Syst., 2018)

Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. - Hanna Soneda; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2019)

A Fault-Tolerant MPSoC For CubeSats. - Christian M. Fuchs; Pai H. Chou; Xiaoqing Wen; Nadia M. Murillo; Gianluca Furano; Stefan Holst; Antonis Tavoularis; Shyue-Kung Lu; Aske Plaat; Kostas Marinis (DFT, 2019)

A Static Method for Analyzing Hotspot Distribution on the LSI. - Kohei Miyase; Yudai Kawano; Shyue-Kung Lu; Xiaoqing Wen; Seiji Kajihara (ITC-Asia, 2019)

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. - Shyue-Kung Lu; Hung-Kai Huang; Chun-Lung Hsu; Chi-Tien Sun; Kohei Miyase (J. Electron. Test., 2019)

ECC Caching Techniques for Protecting NAND Flash Memories. - Shyue-Kung Lu; Zeng-Long Tsai; Chun-Lung Hsu; Chi-Tien Sun (ITC-Asia, 2020)

Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory. - Shyue-Kung Lu; Zeng-Long Tsai; Chun-Lung Hsu; Chi-Tien Sun (VLSI-DAT, 2020)

Fault-Aware Dependability Enhancement Techniques for Flash Memories. - Shyue-Kung Lu; Shu-Chi Yu; Chun-Lung Hsu; Chi-Tien Sun; Masaki Hashizume; Hiroyuki Yotsuyanagi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. - Shyue-Kung Lu; Hui-Ping Li; Kohei Miyase; Chun-Lung Hsu; Chi-Tien Sun (J. Electron. Test., 2021)

Fault Securing Techniques for Yield and Reliability Enhancement of RRAM. - Shyue-Kung Lu; Zhi-Jia Liu; Masaki Hashizume (ATS, 2022)

Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators. - Masao Ohmatsu; Yuto Ohtera; Yuki Ikiri; Hiroyuki Yotsuyanagi; Shyue-Kung Lu; Masaki Hashizume (ATS, 2022)

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. - Taiki Utsunomiya; Ryu Hoshino; Kohei Miyase; Shyue-Kung Lu; Xiaoqing Wen; Seiji Kajihara (ITC-Asia, 2022)

Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories. - Shyue-Kung Lu; Shi-Chun Tseng; Kohei Miyase (ITC, 2022)

Fault Resilience Techniques for Flash Memory of DNN Accelerators. - Shyue-Kung Lu; Yu-Sheng Wu; Jin-Hua Hong; Kohei Miyase (ITC, 2022)

Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory. - Shyue-Kung Lu; Xin Dong (ITC-Asia, 2023)

E3C Techniques for Protecting NAND Flash Memories. - Shyue-Kung Lu; Zeng-Long Tsai (J. Electron. Test., 2023)

Detectability of Resistive Open Defects with Analog Relaxation Oscillators Under Unit-to-Unit Variations of Dies. - Yuya Yamahashi; Yuto Ohtera; Hiroyuki Yotsuyanagi; Shyue-Kung Lu; Masaki Hashizume (3DIC, 2024)

Synergistic Built-In ECC Repair (BIER) Technique for Enhancing Yield and Reliability of Flash Memory. - Shyue-Kung Lu; Chun-Kai Chao; Kohei Miyase (ETS, 2025)