An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3). - Ming-Hwa Sheu; Su-Hon Lin; Chichyang Chen; Shyue-Wen Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

VLSI architecture design for a fast parallel label assignment in binary image. - Shyue-Wen Yang; Ming-Hwa Sheu; Hsien-Huang P. Wu; Hung-En Chien; Ping-Kuo Weng; Ying-Yih Wu (ISCAS (3), 2005)

Fast Fair Crossbar Scheduler for On-chip Router. - Shyue-Wen Yang; Ming-Hwa Sheu; Chun-Kai Yeh; Chih-Yuen Wen; Chih-Chieh Lin; Wen-Kai Tsai (ISCAS, 2007)

Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. - Shyue-Wen Yang; Ming-Hwa Sheu; Jun-Jie Lin; Chuang-Chun Hu; Tzu-Hsiung Chen; Shau-Yin Tseng (IAS, 2009)

FPGA implementation for image object detection system on NoCs. - Ming-Hwa Sheu; Shyue-Wen Yang; Wen-Sheng Huang; Siang-Min Siao (APCCAS, 2010)

Fast image moving object segmentation based on block texture for embedded system implementation. - Shyue-Wen Yang; Ming-Hwa Sheu; Wen-Kai Tsai (ISPACS, 2012)

Extendable multi-pixel object labeling for digital image. - Ming-Hwa Sheu; Shyue-Wen Yang; Tzu-Hsiung Chen (ICCE-TW, 2015)