A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. - Seung-Jun Bae; Young-Soo Sohn; Kwang-Il Park; Kyoung-Ho Kim; Dae-Hyun Chung; Jingook Kim; Si-Hong Kim; Min-Sang Park; Jae-Hyung Lee; Sam-Young Bang; Ho-Kyung Lee; In-Soo Park; et al. (ISSCC, 2008)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)