Canonicalization of threshold logic representation and its applications. - Siang-Yun Lee; Nian-Ze Lee; Jie-Hong R. Jiang (ICCAD, 2018)

Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. - Siang-Yun Lee; Nian-Ze Lee; Jie-Hong R. Jiang (ICCAD, 2019)

Simulation-Guided Boolean Resubstitution. - Siang-Yun Lee; Heinz Riener; Alan Mishchenko; Robert K. Brayton; Giovanni De Micheli (CoRR, 2020)

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. - Eleonora Testa; Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (ASP-DAC, 2021)

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (DDECS, 2021)

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (CoRR, 2021)

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. - Heinz Riener; Siang-Yun Lee; Alan Mishchenko; Giovanni De Micheli (ASP-DAC, 2022)

Beyond local optimality of buffer and splitter insertion for AQFP circuits. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (DAC, 2022)

Majority-based Design Flow for AQFP Superconducting Family. - Giulia Meuli; Vinicius N. Possani; Rajinder Singh; Siang-Yun Lee; Alessandro Tempia Calvino; Dewmini Sudara Marakkalage; Patrick Vuillod; Luca G. Amarù; Scott Chase; Jamil Kawa; Giovanni De Micheli (DATE, 2022)

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (CoRR, 2022)

A Simulation-Guided Paradigm for Logic Synthesis and Verification. - Siang-Yun Lee; Heinz Riener; Alan Mishchenko; Robert K. Brayton; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions. - Hanyu Wang; Siang-Yun Lee; Giovanni De Micheli (CoRR, 2023)

Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization. - Siang-Yun Lee; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration. - Siang-Yun Lee; Alessandro Tempia Calvino; Heinz Riener; Giovanni De Micheli (DAC, 2024)

Technology-Aware Logic Synthesis for Superconducting Electronics. - Rassul Bairamkulov; Siang-Yun Lee; Alessandro Tempia Calvino; Dewmini Sudara Marakkalage; Mingfei Yu; Giovanni De Micheli (DATE, 2024)

Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron. - Siang-Yun Lee; Alessandro Tempia Calvino; Heinz Riener; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. - Fanfan Meng; Siang-Yun Lee; Odysseas Zografos; Mohit Gupta 004; Van D. Nguyen; Giovanni De Micheli; Sorin Cotofana; Inge Asselberghs; Christoph Adelmann; Gouri Sankar Kar; Sebastien Couet; Florin Ciubotaru (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)