Fast Prototyping with Co-operation of Simulation and Emulation. - Siavash Bayat Sarmadi; Seyed Ghassem Miremadi; Ghazanfar Asadi; Ali Reza Ejlali (FPL, 2002)

Speedup analysis in simulation-emulation co-operation. - Seyed Ghassem Miremadi; Siavash Bayat Sarmadi; Ghazanfar Asadi (FPT, 2002)

A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. - Ali Reza Ejlali; Seyed Ghassem Miremadi; Hamid R. Zarandi; Ghazanfar Asadi; Siavash Bayat Sarmadi (DSN, 2003)

Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. - Siavash Bayat Sarmadi; M. Anwar Hasan (DFT, 2005)

Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes. - Siavash Bayat Sarmadi; M. Anwar Hasan (ASAP, 2007)

Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs. - Siavash Bayat Sarmadi; M. Anwar Hasan (ICCD, 2007)

On Concurrent Detection of Errors in Polynomial Basis Multiplication. - Siavash Bayat Sarmadi; M. Anwar Hasan (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures. - Siavash Bayat Sarmadi; M. Anwar Hasan (IEEE Trans. Computers, 2009)

Random data and key generation evaluation of some commercial tokens and smart cards. - Ahmad Boorghany; Siavash Bayat Sarmadi; Pamian Yousefi; Pouneh Gorji; Rasool Jalili (ISCISC, 2014)

Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems. - Mehran Mozaffari Kermani; Kai Tian; Reza Azarderakhsh; Siavash Bayat Sarmadi (IEEE Embed. Syst. Lett., 2014)

Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm. - Siavash Bayat Sarmadi; Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. - Siavash Bayat Sarmadi; Mehran Mozaffari Kermani; Reza Azarderakhsh; Chiou-Yng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m). - Mehran Mozaffari Kermani; Reza Azarderakhsh; Chiou-Yng Lee; Siavash Bayat Sarmadi (IEEE Trans. Very Large Scale Integr. Syst., 2014)

FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. - Behnam Khaleghi; Ali Ahari; Hossein Asadi 001; Siavash Bayat Sarmadi (IEEE Embed. Syst. Lett., 2015)

High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2m) Based on Trinomials. - Siavash Bayat Sarmadi; Mohammad Farmani (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

On Constrained Implementation of Lattice-Based Cryptographic Primitives and Schemes on Smart Cards. - Ahmad Boorghany; Siavash Bayat Sarmadi; Rasool Jalili (ACM Trans. Embed. Comput. Syst., 2015)

Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. - Reza Azarderakhsh; Mehran Mozaffari Kermani; Siavash Bayat Sarmadi; Chiou-Yng Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Efficient Lattice-based Authenticated Encryption: A Practice-Oriented Provable Security Approach. - Ahmad Boorghany; Siavash Bayat Sarmadi; Rasool Jalili (IACR Cryptol. ePrint Arch., 2016)

High-Throughput Low-Complexity Unified Multipliers Over GF(2m) in Dual and Triangular Bases. - Raziyeh Salarifard; Siavash Bayat Sarmadi; Mohammad Farmani (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer. - Mohammad Hossein Yalame; Mohammad Hossein Farzam; Siavash Bayat Sarmadi (ATIS, 2017)

Reliable hardware architectures for efficient secure hash functions ECHO and fugue. - Mehran Mozaffari Kermani; Reza Azarderakhsh; Siavash Bayat Sarmadi (CF, 2018)

Lightweight Hardware Architectures for Efficient Secure Hash Functions ECHO and Fugue. - Mehran Mozaffari Kermani; Reza Azarderakhsh; Siavash Bayat Sarmadi (CoRR, 2018)

A Low-Latency and Low-Complexity Point-Multiplication in ECC. - Raziyeh Salarifard; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE. - Mehran Mozaffari Kermani; Siavash Bayat Sarmadi; A.-Bon E. Ackie; Reza Azarderakhsh (LASCAS, 2019)

A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. - Omid Ranjbar; Siavash Bayat Sarmadi; Fatemeh Pooyan; Hossein Asadi 001 (J. Electron. Test., 2019)

Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT. - Shahriar Ebrahimi; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Internet Things J., 2019)

Toward On-chip Network Security Using Runtime Isolation Mapping. - Mohammad Sadegh Sadeghi; Siavash Bayat Sarmadi; Shaahin Hessabi (ACM Trans. Archit. Code Optim., 2019)

An Efficient Low-Latency Point-Multiplication Over Curve25519. - Raziyeh Salarifard; Siavash Bayat Sarmadi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$. - Taha Shahroodi; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly. - Mohammad Erfan Mazaheri; Farhad Taheri; Siavash Bayat Sarmadi (ISCISC, 2020)

Lightweight and Fault-Resilient Implementations of Binary Ring-LWE for IoT Devices. - Shahriar Ebrahimi; Siavash Bayat Sarmadi (IEEE Internet Things J., 2020)

Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key Encapsulation Using an Efficient Scheduling. - Mohammad Hossein Farzam; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Trans. Circuits Syst., 2020)

Lightweight Fuzzy Extractor Based on LPN for Device and Biometric Authentication in IoT. - Shahriar Ebrahimi; Siavash Bayat Sarmadi (IEEE Internet Things J., 2021)

PLCDefender: Improving Remote Attestation Techniques for PLCs Using Physical Model. - Mohsen Salehi; Siavash Bayat Sarmadi (IEEE Internet Things J., 2021)

A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration. - Nastaran Shekofte; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (ISC Int. J. Inf. Secur., 2021)

Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier. - Mohammad Hossein Farzam; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani; Armin Alivand (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT. - Shahriar Hadayeghparast; Siavash Bayat Sarmadi; Shahriar Ebrahimi (IEEE Internet Things J., 2022)

RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference. - Farhad Taheri; Siavash Bayat Sarmadi; Shahriar Hadayeghparast (IEEE Internet Things J., 2022)

A Study of Timing Side-Channel Attacks and Countermeasures on JavaScript and WebAssembly. - Mohammad Erfan Mazaheri; Siavash Bayat Sarmadi; Farhad Taheri Ardakani (ISC Int. J. Inf. Secur., 2022)

Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier. - Mohammad Hossein Farzam; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani; Armin Alivand (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications. - Farhad Taheri; Siavash Bayat Sarmadi; Shahriar Ebrahimi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Comprehensive Evaluation of RSB and Spectre Vulnerability on Modern Processors. - Farhad Taheri; Siavash Bayat Sarmadi; Alireza Sadeghpour; Seyed Parsa Tayefeh Morsal (CoRR, 2023)

Fixflow: A Framework to Evaluate Fixed-point Arithmetic in Light-Weight CNN Inference. - Farhad Taheri; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani; Reza Taheri (CoRR, 2023)

MISC: Multi-Input Secure Two-Party Computation. - Farhad Taheri Ardakani; Siavash Bayat Sarmadi (ISC Int. J. Inf. Secur., 2023)

PartialHD: Toward Efficient Hyperdimensional Computing by Partial Processing. - Farhad Taheri; Siavash Bayat Sarmadi; Hamed Rastaghi (IEEE Internet Things J., 2024)

A Digital Signature Architecture Suitable for V2V Applications. - Hatameh Mosanaei-Boorani; Siavash Bayat Sarmadi (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)