Static Transition Probability Analysis Under Uncertainty. - Siddharth Garg; Siddharth Tata; Ravishankar Arunachalam (ICCD, 2004)

System-level process-driven variability analysis for single and multiple voltage-frequency island systems. - Diana Marculescu; Siddharth Garg (ICCAD, 2006)

Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. - Siddharth Garg; Diana Marculescu (DATE, 2007)

System-level mitigation of WID leakage power variability using body-bias islands. - Siddharth Garg; Diana Marculescu (CODES+ISSS, 2008)

Voting-based active contour segmentation of fMRI images of the brain. - Gowri Srinivasa; Vivek S. Oak; Siddharth Garg; Matthew C. Fickus; Jelena Kovacevic (ICIP, 2008)

Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems. - Diana Marculescu; Siddharth Garg (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

System-level throughput analysis for process variation aware multiple voltage-frequency island designs. - Siddharth Garg; Diana Marculescu (ACM Trans. Design Autom. Electr. Syst., 2008)

Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective. - Siddharth Garg; Diana Marculescu; Radu Marculescu; Ümit Y. Ogras (DAC, 2009)

System-level process variability analysis and mitigation for 3D MPSoCs. - Siddharth Garg; Diana Marculescu (DATE, 2009)

3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs. - Siddharth Garg; Diana Marculescu (ISQED, 2009)

Process variation aware performance modeling and dynamic power management for multi-core systems. - Siddharth Garg; Diana Marculescu; Sebastian Herbert (ICCAD, 2010)

Custom feedback control: enabling truly scalable on-chip power management for MPSoCs. - Siddharth Garg; Diana Marculescu; Radu Marculescu (ISLPED, 2010)

Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations. - Da-Cheng Juan; Siddharth Garg; Diana Marculescu (DATE, 2011)

Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions. - Siddharth Garg; Diana Marculescu (VTS, 2011)

Robust heterogeneous data center design: a principled approach. - Siddharth Garg; Shreyas Sundaram; Hiren D. Patel (SIGMETRICS Perform. Evaluation Rev., 2011)

Reliable computing with ultra-reduced instruction set co-processors. - Aravindkumar Rajendiran; Sundaram Ananthanarayanan; Hiren D. Patel; Mahesh V. Tripunitara; Siddharth Garg (DAC, 2012)

EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). - Sundaram Ananthanarayanan; Chirag Ravishankar; Siddharth Garg; Andrew A. Kennings (FPGA, 2012)

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. - Chirag Ravishankar; Sundaram Ananthanarayanan; Siddharth Garg; Andrew A. Kennings (FPL, 2012)

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. - Chirag Ravishankar; Sundaram Ananthanarayanan; Siddharth Garg; Andrew A. Kennings (ISQED, 2012)

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip. - Siddharth Garg; Diana Marculescu; Radu Marculescu (ACM J. Emerg. Technol. Comput. Syst., 2012)

On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks. - Siddharth Garg; Diana Marculescu (ACM Trans. Embed. Comput. Syst., 2012)

System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands. - Siddharth Garg; Diana Marculescu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Exploiting Process Variability in Voltage/Frequency Control. - Sebastian Herbert; Siddharth Garg; Diana Marculescu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Resource sharing games with failures and heterogeneous risk attitudes. - Ashish Ranjan Hota; Siddharth Garg; Shreyas Sundaram (Allerton, 2013)

Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling. - Da-Cheng Juan; Siddharth Garg; Jinpyo Park; Diana Marculescu (CODES+ISSS, 2013)

HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors. - Yatish Turakhia; Bharathwaj Raghunathan; Siddharth Garg; Diana Marculescu (DAC, 2013)

Low cost permanent fault detection using ultra-reduced instruction set co-processors. - Sundaram Ananthanarayanan; Siddharth Garg; Hiren D. Patel (DATE, 2013)

Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors. - Bharathwaj Raghunathan; Yatish Turakhia; Siddharth Garg; Diana Marculescu (DATE, 2013)

Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions. - Da-Cheng Juan; Siddharth Garg; Diana Marculescu (ISCAS, 2013)

Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. - Conor O'Sullivan; Peter M. Levine; Siddharth Garg (ISQED, 2013)

Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation. - Frank Imeson; Ariq Emtenan; Siddharth Garg; Mahesh V. Tripunitara (USENIX Security Symposium, 2013)

Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. - Amr M. S. Tosson; Siddharth Garg; Mohab H. Anis (VLSI-SoC, 2013)

A Hybrid Amplitude/Time Encoding Scheme for Enhancing Coding Efficiency and Dynamic Range in Digitally Modulated Power Amplifiers. - Peter Jingjing Xia; Siddharth Garg; Slim Boumaiza (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

Addressing Process Variations at the Microarchitecture and System Level. - Siddharth Garg; Diana Marculescu (Found. Trends Electron. Des. Autom., 2013)

Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits. - Siddharth Garg; Diana Marculescu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era. - Bharathwaj Raghunathan; Siddharth Garg (CODES+ISSS, 2014)

Dark silicon as a challenge for hardware/software co-design. - Muhammad Shafique 001; Siddharth Garg; Tulika Mitra; Sri Parameswaran; Jörg Henkel (CODES+ISSS, 2014)

The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives. - Muhammad Shafique 001; Siddharth Garg; Jörg Henkel; Diana Marculescu (DAC, 2014)

Shielding and securing integrated circuits with sensors. - Davood Shahrjerdi; Jeyavijayan Rajendran; Siddharth Garg; Farinaz Koushanfar; Ramesh Karri (ICCAD, 2014)

An analysis of energy storage and regulation. - Dariush Fooladivanda; Catherine Rosenberg; Siddharth Garg (SmartGridComm, 2014)

State of Charge Evolution Equations for Flywheels. - Dariush Fooladivanda; Guillaume Mancini; Siddharth Garg; Catherine Rosenberg (CoRR, 2014)

Reliable Computing with Ultra-Reduced Instruction Set Coprocessors. - Dan Wang; Aravindkumar Rajendiran; Sundaram Ananthanarayanan; Hiren D. Patel; Mahesh V. Tripunitara; Siddharth Garg (IEEE Micro, 2014)

Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors. - Da-Cheng Juan; Siddharth Garg; Diana Marculescu (ACM Trans. Design Autom. Electr. Syst., 2014)

Variability-aware dark silicon management in on-chip many-core systems. - Muhammad Shafique 001; Dennis Gnad; Siddharth Garg; Jörg Henkel (DATE, 2015)

Energy-efficient computing from systems-on-chip to micro-server and data centers. - Paul Bogdan; Siddharth Garg; Ümit Y. Ogras (IGSC, 2015)

Energy efficient scheduling for web search on heterogeneous microservers. - Sankalp Jain; Harshad Navale; Ümit Y. Ogras; Siddharth Garg (ISLPED, 2015)

Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes. - Mohamed El Massad; Siddharth Garg; Mahesh V. Tripunitara (NDSS, 2015)

Dark Silicon: From Computation to Communication. - Jörg Henkel; Haseeb Bokhari; Siddharth Garg; Muhammad Usman Karim Khan; Heba Khdr; Florian Kriebel; Ümit Y. Ogras; Sri Parameswaran; Muhammad Shafique 001 (NOCS, 2015)

Analysis of energy- and SoC-neutral contracts for frequency regulation with energy storage. - Dariush Fooladivanda; Catherine Rosenberg; Siddharth Garg (SmartGridComm, 2015)

Verifiable ASICs. - Riad S. Wahby; Max Howald; Siddharth Garg; Abhi Shelat; Michael Walfish (IACR Cryptol. ePrint Arch., 2015)

Synergistic timing speculation for multi-threaded programs. - Atif Yasin; Jeff Jun Zhang; Hu Chen; Siddharth Garg; Sanghamitra Roy; Koushik Chakraborty (DAC, 2016)

Can flexible, domain specific programmable logic prevent IP theft? - Xiaotong Cui; Kaijie Wu 001; Siddharth Garg; Ramesh Karri (DFT, 2016)

Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. - Xue Lin 001; Yuankun Xue; Paul Bogdan; Yanzhi Wang; Siddharth Garg; Massoud Pedram (ICCD, 2016)

Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks. - Maria I. Mera Collantes; Mohamed El Massad; Siddharth Garg (ISVLSI, 2016)

Optimal de-anonymization in random graphs with community structure. - Efe Onaran; Siddharth Garg; Elza Erkip (Sarnoff Symposium, 2016)

Non-Deterministic Timers for Hardware Trojan Activation (or How a Little Randomness Can Go the Wrong Way). - Frank Imeson; Saeed Nejati; Siddharth Garg; Mahesh V. Tripunitara (WOOT, 2016)

Thread Progress Equalization: Dynamically Adaptive Power and Performance Optimization of Multi-threaded Applications. - Yatish Turakhia; Guangshuo Liu; Siddharth Garg; Diana Marculescu (CoRR, 2016)

Variability and Reliability Awareness in the Age of Dark Silicon. - Florian Kriebel; Muhammad Shafique 001; Semeen Rehman; Jörg Henkel; Siddharth Garg (IEEE Des. Test, 2016)

Fragility of the commons under prospect-theoretic risk attitudes. - Ashish Ranjan Hota; Siddharth Garg; Shreyas Sundaram (Games Econ. Behav., 2016)

Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling. - Ermao Cai; Da-Cheng Juan; Siddharth Garg; Jinpyo Park; Diana Marculescu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Energy Storage and Regulation: An Analysis. - Dariush Fooladivanda; Catherine Rosenberg; Siddharth Garg (IEEE Trans. Smart Grid, 2016)

Seeded graph matching: Efficient algorithms and theoretical guarantees. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (ACSSC, 2017)

An information theoretic framework for active de-anonymization in social networks based on group memberships. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (Allerton, 2017)

Inspiring trust in outsourced integrated circuit fabrication. - Siddharth Garg (DATE, 2017)

BandiTS: Dynamic timing speculation using multi-armed bandit based optimization. - Jeff Jun Zhang; Siddharth Garg (DATE, 2017)

The Need for Declarative Properties in Digital IC Security. - Mohamed El Massad; Frank Imeson; Siddharth Garg; Mahesh Tripunitara (ACM Great Lakes Symposium on VLSI, 2017)

Optimal checkpointing for secure intermittently-powered IoT devices. - Zahra Ghodsi; Siddharth Garg; Ramesh Karri (ICCAD, 2017)

Reverse engineering camouflaged sequential circuits without scan access. - Mohamed El Massad; Siddharth Garg; Mahesh Tripunitara (ICCAD, 2017)

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. - Abhrajit Sengupta; Satwik Patnaik; Johann Knechtel; Mohammed Ashraf; Siddharth Garg; Ozgur Sinanoglu (ICCAD, 2017)

SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud. - Zahra Ghodsi; Tianyu Gu; Siddharth Garg (NIPS, 2017)

IoT-enabled Distributed Cyber-attacks on Transmission and Distribution Grids. - Yury Dvorkin; Siddharth Garg (CoRR, 2017)

Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism. - Mohamed El Massad; Jun Zhang; Siddharth Garg; Mahesh V. Tripunitara (CoRR, 2017)

BadNets: Identifying Vulnerabilities in the Machine Learning Model Supply Chain. - Tianyu Gu; Brendan Dolan-Gavitt; Siddharth Garg (CoRR, 2017)

Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access. - Mohamed El Massad; Siddharth Garg; Mahesh Tripunitara (CoRR, 2017)

Computing in the Dark Silicon Era: Current Trends and Research Challenges. - Muhammad Shafique 001; Siddharth Garg (IEEE Des. Test, 2017)

Guest Editors' Introduction: Computing in the Dark Silicon Era. - Muhammad Shafique 001; Siddharth Garg; Vikas Chandra (IEEE Des. Test, 2017)

Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications. - Yatish Turakhia; Guangshuo Liu; Siddharth Garg; Diana Marculescu (IEEE Trans. Computers, 2017)

Matching Graphs with Community Structure: A Concentration of Measure Approach. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (Allerton, 2018)

TAO: techniques for algorithm-level obfuscation during high-level synthesis. - Christian Pilato; Francesco Regazzoni 001; Ramesh Karri; Siddharth Garg (DAC, 2018)

Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators. - Jeff Zhang 001; Kartheek Rangineni; Zahra Ghodsi; Siddharth Garg (DAC, 2018)

FATE: fast and accurate timing error prediction framework for low power DNN accelerator design. - Jeff Jun Zhang; Siddharth Garg (ICCAD, 2018)

Typicality Matching for Pairs of Correlated Graphs. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (ISIT, 2018)

Optimal Active social Network De-anonymization Using Information Thresholds. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (ISIT, 2018)

Fine-Pruning: Defending Against Backdooring Attacks on Deep Neural Networks. - Kang Liu 017; Brendan Dolan-Gavitt; Siddharth Garg (RAID, 2018)

Special session: Recent developments in hardware security. - Ro Cammarota; Naghmeh Karimi; Siddharth Garg; Jeyavijayan Rajendran (VTS, 2018)

Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator. - Jeff Jun Zhang; Tianyu Gu; Kanad Basu; Siddharth Garg (VTS, 2018)

Chapter Five - Dynamic Power Management for Dark Silicon Multicore Processors☆. - Siddharth Garg (Adv. Comput., 2018)

ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators. - Jeff Zhang 001; Kartheek Rangineni; Zahra Ghodsi; Siddharth Garg (CoRR, 2018)

Outsourcing Private Machine Learning via Lightweight Secure Arithmetic Computation. - Siddharth Garg; Zahra Ghodsi; Carmit Hazay; Yuval Ishai; Antonio Marcedone; Muthuramakrishnan Venkitasubramaniam (CoRR, 2018)

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. - Christian Pilato; Siddharth Garg; Kaijie Wu 001; Ramesh Karri; Francesco Regazzoni 001 (IEEE Embed. Syst. Lett., 2018)

Building Robust Machine Learning Systems: Current Progress, Research Challenges, and Opportunities. - Jeff Jun Zhang; Kang Liu 017; Faiq Khalid; Muhammad Abdullah Hanif; Semeen Rehman; Theocharis Theocharides; Alessandro Artussi; Muhammad Shafique 001; Siddharth Garg (DAC, 2019)

TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint. - Imran Hafeez Abbassi; Faiq Khalid; Semeen Rehman; Awais Mehmood Kamboh; Axel Jantsch; Siddharth Garg; Muhammad Shafique 001 (DATE, 2019)

Adaptive Adversarial Videos on Roadside Billboards: Dynamically Modifying Trajectories of Autonomous Vehicles. - Naman Patel; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (IROS, 2019)

A Concentration of Measure Approach to Database De-anonymization. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (ISIT, 2019)

BadNets: Evaluating Backdooring Attacks on Deep Neural Networks. - Tianyu Gu; Kang Liu 017; Brendan Dolan-Gavitt; Siddharth Garg (IEEE Access, 2019)

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. - Kang Liu 017; Haoyu Yang; Yuzhe Ma; Benjamin Tan 001; Bei Yu 001; Evangeline F. Y. Young; Ramesh Karri; Siddharth Garg (CoRR, 2019)

Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution. - Jeff Jun Zhang; Kanad Basu; Siddharth Garg (IEEE Des. Test, 2019)

Split Manufacturing-Based Register Transfer-Level Obfuscation. - Xiaotong Cui; Jeff Jun Zhang; Kaijie Wu 001; Siddharth Garg; Ramesh Karri (ACM J. Emerg. Technol. Comput. Syst., 2019)

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. - Christian Pilato; Kaijie Wu 001; Siddharth Garg; Ramesh Karri; Francesco Regazzoni 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

CompAct: On-chip Compression of Activations for Low Power Systolic Array Based CNN Acceleration. - Jeff Jun Zhang; Parul Raj; Shuayb Zarar; Amol Ambardekar; Siddharth Garg (ACM Trans. Embed. Comput. Syst., 2019)

Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots. - Kang Liu 017; Benjamin Tan 001; Ramesh Karri; Siddharth Garg (DATE, 2020)

Is Register Transfer Level Locking Secure? - Chandan Karfa; Ramanuj Chouksey; Christian Pilato; Siddharth Garg; Ramesh Karri (DATE, 2020)

Anomaly Detection in Embedded Systems Using Power and Memory Side Channels. - Jiho Park; Virinchi Roy Surabhi; Prashanth Krishnamurthy; Siddharth Garg; Ramesh Karri; Farshad Khorrami (ETS, 2020)

Model-Switching: Dealing with Fluctuating Workloads in Machine-Learning-as-a-Service Systems. - Jeff Zhang 001; Sameh Elnikety; Shuayb Zarar; Atul Gupta; Siddharth Garg (HotCloud, 2020)

CryptoNAS: Private Inference on a ReLU Budget. - Zahra Ghodsi; Akshaj Kumar Veldanda; Brandon Reagen; Siddharth Garg (NeurIPS, 2020)

SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks. - Maria I. Mera Collantes; Zahra Ghodsi; Siddharth Garg (VTS, 2020)

On the Joint Typicality of Permutations of Sequences of Random Variables. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (CoRR, 2020)

NNoculation: Broad Spectrum and Targeted Treatment of Backdoored DNNs. - Akshaj Kumar Veldanda; Kang Liu 017; Benjamin Tan 001; Prashanth Krishnamurthy; Farshad Khorrami; Ramesh Karri; Brendan Dolan-Gavitt; Siddharth Garg (CoRR, 2020)

Adversarially Robust Learning via Entropic Regularization. - Gauri Jagatap; Animesh Basak Chowdhury; Siddharth Garg; Chinmay Hegde (CoRR, 2020)

On Evaluating Neural Network Backdoor Defenses. - Akshaj Kumar Veldanda; Siddharth Garg (CoRR, 2020)

Detecting Backdoors in Neural Networks Using Novel Feature-Based Anomaly Detection. - Hao Fu; Akshaj Kumar Veldanda; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (CoRR, 2020)

Bait and Switch: Online Training Data Poisoning of Autonomous Driving Systems. - Naman Patel; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (CoRR, 2020)

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators. - Jeff Zhang 001; Zahra Ghodsi; Siddharth Garg; Kartheek Rangineni (IEEE Des. Test, 2020)

Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication. - Maria I. Mera Collantes; Siddharth Garg (IEEE Embed. Syst. Lett., 2020)

The SAT Attack on IC Camouflaging: Impact and Potential Countermeasures. - Mohamed El Massad; Siddharth Garg; Mahesh V. Tripunitara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. - Kang Liu 017; Haoyu Yang; Yuzhe Ma; Benjamin Tan 001; Bei Yu 001; Evangeline F. Y. Young; Ramesh Karri; Siddharth Garg (ACM Trans. Design Autom. Electr. Syst., 2020)

Subverting Privacy-Preserving GANs: Hiding Secrets in Sanitized Images. - Kang Liu 017; Benjamin Tan 001; Siddharth Garg (AAAI, 2021)

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. - Haoyu Yang; Shifan Zhang; Kang Liu 017; Siting Liu 002; Benjamin Tan 001; Ramesh Karri; Siddharth Garg; Bei Yu 001; Evangeline F. Y. Young (ASP-DAC, 2021)

NNoculation: Catching BadNets in the Wild. - Akshaj Kumar Veldanda; Kang Liu 017; Benjamin Tan 001; Prashanth Krishnamurthy; Farshad Khorrami; Ramesh Karri; Brendan Dolan-Gavitt; Siddharth Garg (AISec@CCS, 2021)

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. - Nimisha Limaye; Animesh Basak Chowdhury; Christian Pilato; Mohammed Thari Nabeel; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri (DAC, 2021)

Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP. - Benjamin Tan 001; Siddharth Garg; Ramesh Karri; Yuntao Liu 001; Michael Zuzak; Abhisek Chakraborty; Ankur Srivastava 001; Omid Aramoon; Qian Xu; Gang Qu 001; Adam A. Porter; Jeno Szep; et al. (DAC, 2021)

Vertical IP Protection of the Next-Generation Devices: Quo Vadis? - Shubham Rai; Siddharth Garg; Christian Pilato; Vladimir Herdt; Elmira Moussavi; Dominik Sisejkovic; Ramesh Karri; Rolf Drechsler; Farhad Merchant; Akash Kumar 001 (DATE, 2021)

DeepReDuce: ReLU Reduction for Fast Private Inference. - Nandan Kumar Jha; Zahra Ghodsi; Siddharth Garg; Brandon Reagen (ICML, 2021)

On Graph Matching Using Generalized Seed Side-Information. - Mahshad Shariatnasab; Farhad Shirani 001; Siddharth Garg; Elza Erkip (ISIT, 2021)

Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles. - Zahra Ghodsi; Siva Kumar Sastry Hari; Iuri Frosio; Timothy Tsai 002; Alejandro J. Troccoli; Stephen W. Keckler; Siddharth Garg; Anima Anandkumar (IV, 2021)

Circa: Stochastic ReLUs for Private Deep Learning. - Zahra Ghodsi; Nandan Kumar Jha; Brandon Reagen; Siddharth Garg (NeurIPS, 2021)

Single-Shot Compression for Hypothesis Testing. - Fabrizio Carpi; Siddharth Garg; Elza Erkip (SPAWC, 2021)

Special Section on Attacking and Protecting Artificial Intelligence. - Shivam Bhasin; Siddharth Garg; Francesco Regazzoni 001 (CAAI Trans. Intell. Technol., 2021)

On the Optimization of Behavioral Logic Locking for High-Level Synthesis. - Christian Pilato; Luca Collini; Luca Cassano; Donatella Sciuto; Siddharth Garg; Ramesh Karri (CoRR, 2021)

Sphynx: ReLU-Efficient Network Design for Private Inference. - Minsu Cho; Zahra Ghodsi; Brandon Reagen; Siddharth Garg; Chinmay Hegde (CoRR, 2021)

OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis. - Animesh Basak Chowdhury; Benjamin Tan 001; Ramesh Karri; Siddharth Garg (CoRR, 2021)

Millimeter Wave Wireless-Assisted Robotic Navigation with Link State Classification. - Mingsheng Yin; Akshaj Kumar Veldanda; Amee Trivedi; Jeff Zhang 001; Kai Pfeiffer; Yaqi Hu; Siddharth Garg; Elza Erkip; Ludovic Righetti; Sundeep Rangan (CoRR, 2021)

CryptoNite: Revealing the Pitfalls of End-to-End Private Inference at Scale. - Karthik Garimella; Nandan Kumar Jha; Zahra Ghodsi; Siddharth Garg; Brandon Reagen (CoRR, 2021)

Guest Editors' Introduction: Competing to Secure SoCs. - Siddharth Garg; Daniel E. Holcomb; Jeyavijayan (JV) Rajendran; Ahmad-Reza Sadeghi (IEEE Des. Test, 2021)

Adversarially Robust Learning via Entropic Regularization. - Gauri Jagatap; Ameya Joshi; Animesh Basak Chowdhury; Siddharth Garg; Chinmay Hegde (Frontiers Artif. Intell., 2021)

A Concentration of Measure Approach to Correlated Graph Matching. - Farhad Shirani 001; Siddharth Garg; Elza Erkip (IEEE J. Sel. Areas Inf. Theory, 2021)

Training Data Poisoning in ML-CAD: Backdooring DL-Based Lithographic Hotspot Detectors. - Kang Liu 017; Benjamin Tan 001; Ramesh Karri; Siddharth Garg (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks. - Kang Liu 017; Benjamin Tan 001; Gaurav Rajavendra Reddy; Siddharth Garg; Yiorgos Makris; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

ASSURE: RTL Locking Against an Untrusted Foundry. - Christian Pilato; Animesh Basak Chowdhury; Donatella Sciuto; Siddharth Garg; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Protecting Hardware IP Cores During High-Level Synthesis. - Christian Pilato; Donatella Sciuto; Francesco Regazzoni 001; Siddharth Garg; Ramesh Karri (Behavioral Synthesis for Hardware Security, 2022)

Locked Circuit Indistinguishability: A Notion of Security for Logic Locking. - Mohamed El Massad; Nahid Juma; Jonathan Shahen; Mariana Raykova 001; Siddharth Garg; Mahesh Tripunitara (CSF, 2022)

High-level design methods for hardware security: is it the right choice? invited. - Christian Pilato; Donatella Sciuto; Benjamin Tan 001; Siddharth Garg; Ramesh Karri (DAC, 2022)

Selective Network Linearization for Efficient Private Inference. - Minsu Cho; Ameya Joshi; Brandon Reagen; Siddharth Garg; Chinmay Hegde (ICML, 2022)

Feature Compression for Rate Constrained Object Detection on the Edge. - Zhongzheng Yuan; Samyak Rawlekar; Siddharth Garg; Elza Erkip; Yao Wang 001 (MIPR, 2022)

A Feature-Based On-Line Detector to Remove Adversarial-Backdoors by Iterative Demarcation. - Hao Fu; Akshaj Kumar Veldanda; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (IEEE Access, 2022)

Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis. - Animesh Basak Chowdhury; Benjamin Tan 001; Ryan Carey; Tushit Jain; Ramesh Karri; Siddharth Garg (CoRR, 2022)

Denial-of-Service Attacks on Learned Image Compression. - Kang Liu 017; Di Wu; Yiru Wang; Dan Feng 001; Benjamin Tan 001; Siddharth Garg (CoRR, 2022)

Fairness via In-Processing in the Over-parameterized Regime: A Cautionary Tale. - Akshaj Kumar Veldanda; Ivan Brugere; Jiahao Chen; Sanghamitra Dutta; Alan Mishler; Siddharth Garg (CoRR, 2022)

Security Implications of Large Language Model Code Assistants: A User Study. - Gustavo Sandoval; Hammond Pearce; Teo Nys; Ramesh Karri; Brendan Dolan-Gavitt; Siddharth Garg (CoRR, 2022)

An Upper Bound for the Distribution Overlap Index and Its Applications. - Hao Fu; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (CoRR, 2022)

Sphynx: A Deep Neural Network Design for Private Inference. - Minsu Cho; Zahra Ghodsi; Brandon Reagen; Siddharth Garg; Chinmay Hegde (IEEE Secur. Priv., 2022)

Guest Editorial: Trustworthy AI. - Yier Jin; Tsung-Yi Ho; Stjepan Picek; Siddharth Garg (ACM J. Emerg. Technol. Comput. Syst., 2022)

Millimeter Wave Wireless Assisted Robot Navigation With Link State Classification. - Mingsheng Yin; Akshaj Kumar Veldanda; Amee Trivedi; Jeff Zhang 001; Kai Pfeiffer; Yaqi Hu; Siddharth Garg; Elza Erkip; Ludovic Righetti; Sundeep Rangan (IEEE Open J. Commun. Soc., 2022)

Robust Deep Learning for IC Test Problems. - Animesh Basak Chowdhury; Benjamin Tan 001; Siddharth Garg; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Overriding Autonomous Driving Systems Using Adaptive Adversarial Billboards. - Naman Patel; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (IEEE Trans. Intell. Transp. Syst., 2022)

Lost at C: Data from the Security-focused User Study. - Gustavo Sandoval; Hammond Pearce; Teo Nys; Ramesh Karri; Siddharth Garg; Brendan Dolan-Gavitt (Zenodo, 2022)

Characterizing and Optimizing End-to-End Systems for Private Inference. - Karthik Garimella; Zahra Ghodsi; Nandan Kumar Jha; Siddharth Garg; Brandon Reagen (ASPLOS (3), 2023)

Special Session: Machine Learning for Embedded System Design. - Erika S. Alcorta; Andreas Gerstlauer; Chenhui Deng; Qi Sun; Zhiru Zhang; Ceyu Xu; Lisa Wu Wills; Daniela Sanchez Lopera; Wolfgang Ecker; Siddharth Garg; Jiang Hu (CODES+ISSS, 2023)

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. - Animesh Basak Chowdhury; Lilas Alrahis; Luca Collini; Johann Knechtel; Ramesh Karri; Siddharth Garg; Ozgur Sinanoglu; Benjamin Tan 001 (DAC, 2023)

Benchmarking Large Language Models for Automated Verilog RTL Code Generation. - Shailja Thakur; Baleegh Ahmad; Zhenxing Fan; Hammond Pearce; Benjamin Tan 001; Ramesh Karri; Brendan Dolan-Gavitt; Siddharth Garg (DATE, 2023)

Precoding-oriented Massive MIMO CSI Feedback Design. - Fabrizio Carpi; Sivarama Venkatesan; Jinfeng Du; Harish Viswanathan; Siddharth Garg; Elza Erkip (ICC, 2023)

Invited Paper: Towards the Imagenets of ML4EDA. - Animesh Basak Chowdhury; Shailja Thakur; Hammond Pearce; Ramesh Karri; Siddharth Garg (ICCAD, 2023)

Path Planning Under Uncertainty to Localize mmWave Sources. - Kai Pfeiffer; Yuze Jia; Mingsheng Yin; Akshaj Kumar Veldanda; Yaqi Hu; Amee Trivedi; Jeff Zhang 001; Siddharth Garg; Elza Erkip; Sundeep Rangan; Ludovic Righetti (ICRA, 2023)

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design. - Jason Blocklove; Siddharth Garg; Ramesh Karri; Hammond Pearce (MLCAD, 2023)

ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations. - Animesh Basak Chowdhury; Jitendra Bhandari; Luca Collini; Ramesh Karri; Benjamin Tan 001; Siddharth Garg (MLCAD, 2023)

Exploiting Connections between Lipschitz Structures for Certifiably Robust Deep Equilibrium Models. - Aaron J. Havens; Alexandre Araujo; Siddharth Garg; Farshad Khorrami; Bin Hu 002 (NeurIPS, 2023)

Towards better certified segmentation via diffusion models. - Othmane Laousy; Alexandre Araujo; Guillaume Chassagnon; Marie-Pierre Revel; Siddharth Garg; Farshad Khorrami; Maria Vakalopoulou (UAI, 2023)

Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants. - Gustavo Sandoval; Hammond Pearce; Teo Nys; Ramesh Karri; Siddharth Garg; Brendan Dolan-Gavitt (USENIX Security Symposium, 2023)

Can Deepfakes be created on a whim? - Pulak Mehta; Gauri Jagatap; Kevin Gallagher 001; Brian Timmerman; Progga Deb; Siddharth Garg; Rachel Greenstadt; Brendan Dolan-Gavitt (WWW (Companion Volume), 2023)

A Minimax Approach Against Multi-Armed Adversarial Attacks Detection. - Federica Granese; Marco Romanelli 002; Siddharth Garg; Pablo Piantanida (CoRR, 2023)

Can deepfakes be created by novice users? - Pulak Mehta; Gauri Jagatap; Kevin Gallagher 001; Brian Timmerman; Progga Deb; Siddharth Garg; Rachel Greenstadt; Brendan Dolan-Gavitt (CoRR, 2023)

INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search. - Animesh Basak Chowdhury; Marco Romanelli 002; Benjamin Tan 001; Ramesh Karri; Siddharth Garg (CoRR, 2023)

R-LPIPS: An Adversarially Robust Perceptual Similarity Metric. - Sara Ghazanfari; Siddharth Garg; Prashanth Krishnamurthy; Farshad Khorrami; Alexandre Araujo (CoRR, 2023)

PriViT: Vision Transformers for Fast Private Inference. - Naren Dhyani; Jianqiao Mo; Minsu Cho; Ameya Joshi; Siddharth Garg; Brandon Reagen; Chinmay Hegde (CoRR, 2023)

Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT. - Akshaj Kumar Veldanda; Fabian Grob; Shailja Thakur; Hammond Pearce; Benjamin Tan 001; Ramesh Karri; Siddharth Garg (CoRR, 2023)

Towards the Imagenets of ML4EDA. - Animesh Basak Chowdhury; Shailja Thakur; Hammond Pearce; Ramesh Karri; Siddharth Garg (CoRR, 2023)

AutoChip: Automating HDL Generation Using LLM Feedback. - Shailja Thakur; Jason Blocklove; Hammond Pearce; Benjamin Tan 001; Siddharth Garg; Ramesh Karri (CoRR, 2023)

Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis. - Animesh Basak Chowdhury; Benjamin Tan 001; Ryan Carey; Tushit Jain; Ramesh Karri; Siddharth Garg (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Differential Analysis of Triggers and Benign Features for Black-Box DNN Backdoor Detection. - Hao Fu; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (IEEE Trans. Inf. Forensics Secur., 2023)

Fairness via In-Processing in the Over-parameterized Regime: A Cautionary Tale with MinDiff Loss. - Akshaj Kumar Veldanda; Ivan Brugere; Jiahao Chen; Sanghamitra Dutta; Alan Mishler; Siddharth Garg (Trans. Mach. Learn. Res., 2023)

Optimizing the Use of Behavioral Locking for High-Level Synthesis. - Christian Pilato; Luca Collini; Luca Cassano; Donatella Sciuto; Siddharth Garg; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Lost at C: Data from the Security-focused User Study. - Gustavo Sandoval; Hammond Pearce; Teo Nys; Ramesh Karri; Siddharth Garg; Brendan Dolan-Gavitt (Zenodo, 2023)

SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs. - Alhad Daftardar; Brandon Reagen; Siddharth Garg (PACT, 2024)

On the (In)feasibility of ML Backdoor Detection as an Hypothesis Testing Problem. - Georg Pichler; Marco Romanelli 002; Divya Prakash Manivannan; Prashanth Krishnamurthy; Farshad Khorrami; Siddharth Garg (AISTATS, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (ICCAD, 2024)

Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization. - Animesh Basak Chowdhury; Marco Romanelli 002; Benjamin Tan 001; Ramesh Karri; Siddharth Garg (ICLR, 2024)

LipSim: A Provably Robust Perceptual Similarity Metric. - Sara Ghazanfari; Alexandre Araujo; Prashanth Krishnamurthy; Farshad Khorrami; Siddharth Garg (ICLR, 2024)

Novel Quadratic Constraints for Extending LipSDP beyond Slope-Restricted Activations. - Patricia Pauli; Aaron J. Havens; Alexandre Araujo; Siddharth Garg; Farshad Khorrami; Frank Allgöwer; Bin Hu 002 (ICLR, 2024)

Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design. - Andre Nakkab; Sai Qian Zhang; Ramesh Karri; Siddharth Garg (MLCAD, 2024)

NYU CTF Bench: A Scalable Open-Source Benchmark Dataset for Evaluating LLMs in Offensive Security. - Minghao Shao; Sofija Jancheska; Meet Udeshi; Brendan Dolan-Gavitt; Haoran Xi; Kimberly Milner; Boyuan Chen 004; Max Yin; Siddharth Garg; Prashanth Krishnamurthy; Farshad Khorrami; Ramesh Karri; et al. (NeurIPS, 2024)

Learned Pulse Shaping Design for PAPR Reduction in DFT-s-OFDM. - Fabrizio Carpi; Soheil Rostami; Joonyoung Cho; Siddharth Garg; Elza Erkip; Charlie Jianzhong Zhang (SPAWC, 2024)

Neural Compress-and-Forward for the Relay Channel. - Ezgi Özyilkan; Fabrizio Carpi; Siddharth Garg; Elza Erkip (SPAWC, 2024)

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS. - Matthew DeLorenzo; Animesh Basak Chowdhury; Vasudev Gohil; Shailja Thakur; Ramesh Karri; Siddharth Garg; Jeyavijayan Rajendran (CoRR, 2024)

An Empirical Evaluation of LLMs for Solving Offensive Security Challenges. - Minghao Shao; Boyuan Chen 004; Sofija Jancheska; Brendan Dolan-Gavitt; Siddharth Garg; Ramesh Karri; Muhammad Shafique 001 (CoRR, 2024)

Evaluating LLMs for Hardware Design and Test. - Jason Blocklove; Siddharth Garg; Ramesh Karri; Hammond Pearce (CoRR, 2024)

Model Cascading for Code: Reducing Inference Costs with Model Cascading for LLM Based Code Generation. - Boyuan Chen 004; Mingzhi Zhu; Brendan Dolan-Gavitt; Muhammad Shafique 001; Siddharth Garg (CoRR, 2024)

NYU CTF Dataset: A Scalable Open-Source Benchmark Dataset for Evaluating LLMs in Offensive Security. - Minghao Shao; Sofija Jancheska; Meet Udeshi; Brendan Dolan-Gavitt; Haoran Xi; Kimberly Milner; Boyuan Chen 004; Max Yin; Siddharth Garg; Prashanth Krishnamurthy; Farshad Khorrami; Ramesh Karri; et al. (CoRR, 2024)

C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap? - Luca Collini; Siddharth Garg; Ramesh Karri (CoRR, 2024)

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines. - Jitendra Bhandari; Johann Knechtel; Ramesh Narayanaswamy; Siddharth Garg; Ramesh Karri (CoRR, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Mohammed Nabeel 001; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (CoRR, 2024)

Can EDA Tool Feedback Improve Verilog Generation by LLMs? - Jason Blocklove; Shailja Thakur; Benjamin Tan 001; Hammond Pearce; Siddharth Garg; Ramesh Karri (CoRR, 2024)

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI. - Jitendra Bhandari; Vineet Bhat; Yuheng He; Siddharth Garg; Hamed Rahmani; Ramesh Karri (CoRR, 2024)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap. - Luca Collini; Siddharth Garg; Ramesh Karri (CoRR, 2024)

TruncFormer: Private LLM Inference Using Only Truncations. - Patrick Yubeaton; Jianqiao Mo; Karthik Garimella; Nandan Kumar Jha; Brandon Reagen; Chinmay Hegde; Siddharth Garg (CoRR, 2024)

PrefixLLM: LLM-aided Prefix Circuit Design. - Weihua Xiao; Venkata Sai Charan Putrevu; Raghu Vamshi Hemadri; Siddharth Garg; Ramesh Karri (CoRR, 2024)

Out-of-Distribution Detection with Overlap Index. - Hao Fu; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (CoRR, 2024)

Towards Unified Benchmark and Models for Multi-Modal Perceptual Metrics. - Sara Ghazanfari; Siddharth Garg; Nicolas Flammarion; Prashanth Krishnamurthy; Farshad Khorrami; Francesco Croce (CoRR, 2024)

Privacy-Preserving Collaborative Learning Through Feature Extraction. - Alireza Sarmadi; Hao Fu; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (IEEE Trans. Dependable Secur. Comput., 2024)

PriViT: Vision Transformers for Private Inference. - Naren Dhyani; Jianqiao Cambridge Mo; Patrick Yubeaton; Minsu Cho; Ameya Joshi; Siddharth Garg; Brandon Reagen; Chinmay Hegde (Trans. Mach. Learn. Res., 2024)

Hyper-parameter Tuning for Fair Classification without Sensitive Attribute Access. - Akshaj Kumar Veldanda; Ivan Brugere; Sanghamitra Dutta; Alan Mishler; Siddharth Garg (Trans. Mach. Learn. Res., 2024)

Split Computing With Scalable Feature Compression for Visual Analytics on the Edge. - Zhongzheng Yuan; Samyak Rawlekar; Siddharth Garg; Elza Erkip; Yao Wang 001 (IEEE Trans. Multim., 2024)

VeriGen: A Large Language Model for Verilog Code Generation. - Shailja Thakur; Baleegh Ahmad; Hammond Pearce; Benjamin Tan 001; Brendan Dolan-Gavitt; Ramesh Karri; Siddharth Garg (ACM Trans. Design Autom. Electr. Syst., 2024)

Manipulation Attacks on Learned Image Compression. - Kang Liu 017; Di Wu; Yangyu Wu 003; Yiru Wang; Dan Feng 001; Benjamin Tan 001; Siddharth Garg (IEEE Trans. Artif. Intell., 2024)

Large Language Models (LLMs) for Verification, Testing, and Design. - Chandan Kumar Jha 001; Muhammad Hassan 001; Khushboo Qayyum; Sallar Ahmadi-Pour; Kangwei Xu; Ruidi Qiu; Jason Blocklove; Luca Collini; Andre Nakkab; Ulf Schlichtmann; Grace Li Zhang; Ramesh Karri; et al. (ETS, 2025)

Detecting All-to-One Backdoor Attacks in Black-Box DNNs via Differential Robustness to Noise. - Hao Fu; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (IEEE Access, 2025)

Need for zkSpeed: Accelerating HyperPlonk for Zero-Knowledge Proofs. - Alhad Daftardar; Jianqiao Mo; Joey Ah-kiow; Benedikt Bünz; Ramesh Karri; Siddharth Garg; Brandon Reagen (IACR Cryptol. ePrint Arch., 2025)

EMMA: Efficient Visual Alignment in Multi-Modal LLMs. - Sara Ghazanfari; Alexandre Araujo; Prashanth Krishnamurthy; Siddharth Garg; Farshad Khorrami (Trans. Mach. Learn. Res., 2025)

Uncertainty-Aware Deep Neural Representations for Visual Analysis of Vector Field Data. - Atul Kumar; Siddharth Garg; Soumya Dutta (IEEE Trans. Vis. Comput. Graph., 2025)

Huff-LLM: End-to-End Lossless Compression for Efficient LLM Inference. - Patrick Yubeaton; Tareq Mahmoud; Shehab Naga; Pooria Taheri; Tianhua Xia; Arun George; Yasmein Khalil; Sai Qian Zhang; Siddharth Joshi 001; Chinmay Hegde; Siddharth Garg (CoRR, 2025)

Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective. - Luca Collini; Andrew Hennessee; Ramesh Karri; Siddharth Garg (CoRR, 2025)

VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification. - Patrick Yubeaton; Andre Nakkab; Weihua Xiao; Luca Collini; Ramesh Karri; Chinmay Hegde; Siddharth Garg (CoRR, 2025)

Chain-of-Frames: Advancing Video Understanding in Multimodal LLMs via Frame-Aware Reasoning. - Sara Ghazanfari; Francesco Croce; Nicolas Flammarion; Prashanth Krishnamurthy; Farshad Khorrami; Siddharth Garg (CoRR, 2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code. - Raghu Vamshi Hemadri; Jitendra Bhandari; Andre Nakkab; Johann Knechtel; Badri P. Gopalan; Ramesh Narayanaswamy; Ramesh Karri; Siddharth Garg (CoRR, 2025)

Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA. - Weihua Xiao; Derek Ekberg; Siddharth Garg; Ramesh Karri (CoRR, 2025)

MetaCipher: A General and Extensible Reinforcement Learning Framework for Obfuscation-Based Jailbreak Attacks on Black-Box LLMs. - Boyuan Chen 004; Minghao Shao; Abdul Basit; Siddharth Garg; Muhammad Shafique 001 (CoRR, 2025)

MTU: The Multifunction Tree Unit in zkSpeed for Accelerating HyperPlonk. - Jianqiao Mo; Alhad Daftardar; Joey Ah-kiow; Kaiyue Guo; Benedikt Bünz; Siddharth Garg; Brandon Reagen (CoRR, 2025)

Learning-Based Compress-and-Forward Schemes for the Relay Channel. - Ezgi Özyilkan; Fabrizio Carpi; Siddharth Garg; Elza Erkip (IEEE J. Sel. Areas Commun., 2025)